Got rid of ftw_we and tested on hw with freq sweep

rtl/toplevel/top_generic.v

@@ -15,16 +15,38 @@ module top_generic(
     assign led_green = 1'b0;
     assign led_red = 1'b0;
 
+
+    reg [11:0] count;
+    localparam integer DIV_MAX = 100_000 - 1; // 1 ms tick at 100 MHz
+    reg [16:0] div_counter = 0;               // enough bits for 100k (2^17=131072)
+    always @(posedge aclk) begin
+        if (!aresetn) begin
+            div_counter <= 0;
+            count <= 0;
+        end else begin
+            if (div_counter == DIV_MAX) begin
+                div_counter <= 0;
+                if (count == 12'd3999)
+                    count <= 0;               // wrap at 4000
+                else
+                    count <= count + 1'b1;    // increment every 1 ms
+            end else begin
+                div_counter <= div_counter + 1'b1;
+            end
+        end
+    end
+
+
     wire [15:0] sin_q15;
     wire clk_en;
     nco_q15 #(
         .CLK_HZ(100_000_000),
-        .PHASE_BITS(16)
+        .PHASE_BITS(16),
+        .FS_HZ(40_000)
     ) nco (
         .clk    (aclk),
         .rst_n  (aresetn),
-        .ftw_in (32'h0),
-        .ftw_we (1'b0),
+        .ftw_in (ftw_from_hz(count, 16, 40_000)),
         .sin_q15(sin_q15),
         .cos_q15(),
         .clk_en (clk_en)
@@ -37,9 +59,9 @@ module top_generic(
     wire [5:0] dac_code_next = biased[15:10];     // 0..63 (MSB=bit5)
     // Register it at the sample rate (clk_en)
     reg [5:0] dac_code;
-    always @(posedge aclk or negedge aresetn) begin
+    always @(posedge aclk) begin
         if (!aresetn) dac_code <= 6'd0;
-        else if (clk_en) dac_code <= dac_code_next;
+        else dac_code <= dac_code_next;
     end
     assign r2r = dac_code;
 endmodule