Added everything from the other system

2026-02-28 21:46:59 +01:00
parent 907f244b24
commit 1c37d384c2
34 changed files with 1601 additions and 57 deletions
--- a/cores/system/test/test.core
+++ b/cores/system/test/test.core
@@ -7,12 +7,18 @@ filesets:
    rtl:
        depend:
            - joppeb:primitive:clkgen
-            - joppeb:wb:jtag_wb_bridge
-            - joppeb:wb:wb_gpio
+            - joppeb:system:mcu
+            - joppeb:signal:nco_q15
+            - joppeb:util:conv
        files:
            - rtl/toplevel.v
        file_type: verilogSource

+    sw:
+        files:
+            - sw/sweep/sweep.hex
+        file_type: user
+
    mimas:
        files:
            - mimas.ucf : {file_type : UCF}
@@ -28,6 +34,7 @@ targets:
        filesets:
            - rtl
            - mimas
+            - sw
        toplevel: toplevel
        parameters:
            - FPGA_SPARTAN6=true