jtag memory interface working
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196
rtl/wb/jtag_wb_bridge.v
Normal file
196
rtl/wb/jtag_wb_bridge.v
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@@ -0,0 +1,196 @@
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`timescale 1ns/1ps
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module jtag_wb_bridge #(
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parameter integer chain = 1,
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// 0: Use cmd_addr[1:0] to select byte lane on 32-bit WB data bus.
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// 1: Always use lane 0 (LSB), for byte-wide memories that return data in [7:0].
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parameter integer byte_aligned = 0
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)(
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input wire i_clk,
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input wire i_rst,
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output wire [31:0] o_wb_adr,
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output wire [31:0] o_wb_dat,
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output wire [3:0] o_wb_sel,
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output wire o_wb_we,
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output wire o_wb_cyc,
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output wire o_wb_stb,
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input wire [31:0] i_wb_rdt,
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input wire i_wb_ack,
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output wire o_cmd_reset
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);
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// JTAG interface wires
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wire jtag_tck;
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wire jtag_tdi;
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wire jtag_drck;
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wire jtag_capture;
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wire jtag_shift;
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wire jtag_update;
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wire jtag_runtest;
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wire jtag_reset;
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wire jtag_sel;
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reg [41:0] jtag_q;
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wire [41:0] jtag_data_in;
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wire jtag_async_reset;
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jtag_if #(
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.chain(chain)
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) jtag (
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.i_tdo(jtag_q[0]),
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.o_tck(jtag_tck),
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.o_tdi(jtag_tdi),
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.o_drck(jtag_drck),
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.o_capture(jtag_capture),
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.o_shift(jtag_shift),
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.o_update(jtag_update),
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.o_runtest(jtag_runtest),
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.o_reset(jtag_reset),
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.o_sel(jtag_sel)
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);
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assign jtag_async_reset = jtag_reset || i_rst;
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// JTAG shift register behavior
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always @(posedge jtag_drck or posedge jtag_async_reset) begin
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if (jtag_async_reset) begin
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jtag_q <= 42'b0;
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end else if (jtag_sel && jtag_capture) begin
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jtag_q <= jtag_data_in;
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end else if (jtag_sel && jtag_shift) begin
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jtag_q <= {jtag_tdi, jtag_q[41:1]};
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end
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end
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// -----------------------------------------------------------------------------
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// JTAG -> i_clk crossing using toggle request/ack handshake.
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// Command packet format: [41]=we, [40]=reset, [39:8]=addr, [7:0]=wdata
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// -----------------------------------------------------------------------------
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reg [41:0] j_cmd_hold;
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reg j_req_tgl;
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reg j_ack_sync_1;
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reg j_ack_sync_2;
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reg s_ack_tgl;
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reg s_req_sync_1;
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reg s_req_sync_2;
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reg s_req_sync_3;
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reg [41:0] s_cmd_sync_1;
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reg [41:0] s_cmd_sync_2;
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always @(posedge jtag_drck or posedge jtag_async_reset) begin
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if (jtag_async_reset) begin
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j_ack_sync_1 <= 1'b0;
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j_ack_sync_2 <= 1'b0;
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end else begin
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j_ack_sync_1 <= s_ack_tgl;
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j_ack_sync_2 <= j_ack_sync_1;
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end
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end
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always @(posedge jtag_update or posedge jtag_async_reset) begin
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if (jtag_async_reset) begin
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j_cmd_hold <= 42'b0;
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j_req_tgl <= 1'b0;
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end else if (jtag_sel && (j_ack_sync_2 == j_req_tgl)) begin
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j_cmd_hold <= jtag_q;
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j_req_tgl <= ~j_req_tgl;
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end
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end
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// -----------------------------------------------------------------------------
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// Wishbone classic single-request master (1 outstanding transaction max).
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// -----------------------------------------------------------------------------
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reg wb_busy;
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reg [31:0] wb_adr_r;
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reg [31:0] wb_dat_r;
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reg [3:0] wb_sel_r;
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reg wb_we_r;
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reg cmd_reset_pulse_r;
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reg [31:0] resp_addr_r;
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reg [7:0] resp_data_r;
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wire req_pulse;
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wire [7:0] cmd_wdata;
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wire [31:0] cmd_addr;
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wire cmd_reset;
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wire cmd_we;
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wire [1:0] req_lane;
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wire [1:0] resp_lane;
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assign req_pulse = s_req_sync_2 ^ s_req_sync_3;
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assign cmd_wdata = s_cmd_sync_2[7:0];
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assign cmd_addr = s_cmd_sync_2[39:8];
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assign cmd_reset = s_cmd_sync_2[40];
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assign cmd_we = s_cmd_sync_2[41];
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assign req_lane = byte_aligned ? 2'b00 : cmd_addr[1:0];
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assign resp_lane = byte_aligned ? 2'b00 : wb_adr_r[1:0];
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assign o_wb_adr = wb_adr_r;
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assign o_wb_dat = wb_dat_r;
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assign o_wb_sel = wb_sel_r;
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assign o_wb_we = wb_we_r;
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assign o_wb_cyc = wb_busy;
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assign o_wb_stb = wb_busy;
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assign o_cmd_reset = cmd_reset_pulse_r;
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always @(posedge i_clk) begin
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if (i_rst) begin
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s_ack_tgl <= 1'b0;
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s_req_sync_1 <= 1'b0;
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s_req_sync_2 <= 1'b0;
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s_req_sync_3 <= 1'b0;
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s_cmd_sync_1 <= 42'b0;
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s_cmd_sync_2 <= 42'b0;
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wb_busy <= 1'b0;
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wb_adr_r <= 32'b0;
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wb_dat_r <= 32'b0;
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wb_sel_r <= 4'b0000;
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wb_we_r <= 1'b0;
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cmd_reset_pulse_r <= 1'b0;
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resp_addr_r <= 32'b0;
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resp_data_r <= 8'b0;
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end else begin
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s_req_sync_1 <= j_req_tgl;
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s_req_sync_2 <= s_req_sync_1;
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s_req_sync_3 <= s_req_sync_2;
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s_cmd_sync_1 <= j_cmd_hold;
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s_cmd_sync_2 <= s_cmd_sync_1;
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cmd_reset_pulse_r <= 1'b0;
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if (req_pulse && !wb_busy) begin
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wb_busy <= 1'b1;
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wb_we_r <= cmd_we;
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wb_adr_r <= cmd_addr;
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case (req_lane)
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2'b00: begin wb_sel_r <= 4'b0001; wb_dat_r <= {24'b0, cmd_wdata}; end
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2'b01: begin wb_sel_r <= 4'b0010; wb_dat_r <= {16'b0, cmd_wdata, 8'b0}; end
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2'b10: begin wb_sel_r <= 4'b0100; wb_dat_r <= {8'b0, cmd_wdata, 16'b0}; end
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default: begin wb_sel_r <= 4'b1000; wb_dat_r <= {cmd_wdata, 24'b0}; end
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endcase
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cmd_reset_pulse_r <= cmd_reset;
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end
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if (wb_busy && i_wb_ack) begin
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wb_busy <= 1'b0;
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wb_we_r <= 1'b0;
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resp_addr_r <= wb_adr_r;
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case (resp_lane)
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2'b00: resp_data_r <= i_wb_rdt[7:0];
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2'b01: resp_data_r <= i_wb_rdt[15:8];
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2'b10: resp_data_r <= i_wb_rdt[23:16];
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default: resp_data_r <= i_wb_rdt[31:24];
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endcase
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s_ack_tgl <= s_req_sync_2;
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end
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end
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end
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assign jtag_data_in = {2'b00, resp_addr_r, resp_data_r};
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endmodule
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