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jtag memory interface working

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Joppe Blondel
2026-02-25 16:14:37 +01:00
parent 9930ce4461
commit 13f72e698f
10 changed files with 664 additions and 358 deletions
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21
project.cfg
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@@ -21,7 +21,7 @@ device = xc6slx9
package = tqg144
speedgrade = -2
toplevel = top_generic
xst_opts = -vlgincdir rtl/util -keep_hierarchy yes
xst_opts = -vlgincdir rtl/util
files_verilog = rtl/util/conv.vh
rtl/toplevel/top_generic.v
rtl/core/nco_q15.v
@@ -57,9 +57,10 @@ files_verilog = rtl/util/conv.vh
rtl/serv/servile.v
rtl/serv/serving_ram.v
rtl/serv/serving.v
rtl/arch/spartan-6/jtag_if.v
rtl/wb/wb_gpio.v
rtl/wb/wb_gpio_banks.v
rtl/arch/spartan-6/jtag_if.v
rtl/wb/jtag_wb_bridge.v
rtl/core/mcu.v
files_con = boards/mimas_v1/constraints.ucf
files_other = rtl/util/rc_alpha_q15.vh
@@ -74,11 +75,13 @@ device = xc6slx9
package = tqg144
speedgrade = -2
toplevel = top_jtag
xst_opts = -vlgincdir rtl/util
xst_opts = -vlgincdir rtl/util -keep_hierarchy yes
files_other =
files_con = boards/mimas_v1/constraints.ucf
files_verilog = rtl/arch/spartan-6/jtag_if.v
rtl/arch/spartan-6/clk_gen.v
rtl/wb/jtag_wb_bridge.v
rtl/wb/wb_gpio.v
rtl/toplevel/top_jtag.v
[target.svftest]
@@ -87,4 +90,16 @@ runtime = all
toplevel = tb_svf
files_verilog = sim/tb/tb_svf.v
sim/overrides/jtag_if.v
rtl/core/cdc_strobed.v
files_other = sim/other/test.svf
[target.tools]
toolchain = make
output_files = tools/test
buildroot = tools
files_makefile = tools/Makefile
files_other = tools/digilent_jtag.cpp
tools/digilent_jtag.hpp
tools/argparse.cpp
tools/argparse.hpp
tools/test.cpp