Added back in the jtag bridge

Now talking over the bus instead of using dpram

rtl/core/mcu_peripherals.v

@@ -14,13 +14,16 @@ module mcu_peripherals (
 
     input wire [4*32-1:0] i_gpio,
     output wire [4*32-1:0] o_gpio,
-    output wire o_timer_irq
+    output wire o_timer_irq,
+    output wire o_core_reset
 );
     localparam [31:0] GPIO_BASE_ADDR = 32'h4000_0000;
     localparam [31:0] GPIO_ADDR_MASK = 32'hFFFF_0000;
     localparam [31:0] TIMER_BASE_ADDR = 32'h4001_0000;
     localparam [31:0] TIMER_ADDR_MASK = 32'hFFFF_0000;
 
+    assign o_core_reset = 1'b0;
+
     wire [2*32-1:0] wbs_adr;
     wire [2*32-1:0] wbs_dat_w;
     wire [2*4-1:0] wbs_sel;