Added back in the jtag bridge

Now talking over the bus instead of using dpram

project.cfg

@@ -133,7 +133,7 @@ device              = xc6slx9
 package             = tqg144
 speedgrade          = -2
 toplevel            = top_generic
-xst_opts            = -vlgincdir rtl/util
+xst_opts            = -vlgincdir rtl/util -keep_hierarchy yes
 files_verilog       = rtl/toplevel/top_generic.v
                       rtl/util/conv.vh
                       rtl/core/nco_q15.v
@@ -147,6 +147,7 @@ files_verilog       = rtl/toplevel/top_generic.v
                       rtl/core/cdc_strobe_data.v
                       rtl/core/cdc_req_resp.v
                       rtl/core/mcu.v
+                      rtl/core/arbiter.v
                       rtl/core/mem_jtag_writable.v
                     # Arch
                       rtl/arch/spartan-6/lvds_comparator.v
@@ -190,6 +191,7 @@ files_verilog       = rtl/toplevel/top_generic.v
                       rtl/wb/wb_gpio.v
                       rtl/wb/wb_gpio_banks.v
                       rtl/wb/wb_mux.v
+                      rtl/wb/wb_arbiter.v
                       rtl/wb/jtag_wb_bridge.v
                       rtl/wb/wb_timer.v