12 lines
601 B
Markdown
12 lines
601 B
Markdown
# ZYNQ 7 series project
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### Basic FPGA workflow
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+ target `ip`: Generate IP blocks defined in the tcl files in the IP directory
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+ target `synth`: Synthesize design
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+ target `sim`: Behavioural simulation of part of the design
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+ target `psim`: Post synthesis simulation of mentioned part of the design
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### ZYNQ SoC workflos
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+ target `firmware`: Compile the firmware running on the ARM core(s) with the `make` toolchain
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+ target `firmsim`: Simulate the firmware with QEMU without PS/PL cosimulation with the `qemu` toolchain
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+ target `devtree`: Compile the device tree for a PS/PL cosimulation with QEMU |