38 lines
1.0 KiB
VHDL
38 lines
1.0 KiB
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.NUMERIC_STD.all;
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entity tb_toplevel is
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end entity;
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architecture behavioural of tb_toplevel is
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-- COMPONENTS
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-- ----------
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component toplevel is
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port (
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ACLK : in std_logic;
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LED : out std_logic_vector(7 downto 0);
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SW : in std_logic_vector(3 downto 0)
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);
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end component;
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-- SIGNALS
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-- -------
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signal ACLK : std_logic := '0';
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signal LED : std_logic_vector(7 downto 0) := "00000000";
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signal SW : std_logic_vector(3 downto 0) := "0111";
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begin
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c_toplevel : component toplevel port map(
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ACLK, LED, SW
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);
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ACLK <= not ACLK after 10 ns;
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SW(3) <= '1' after 150 ns;
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process
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begin
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wait until SW(3)='1';
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SW(2 downto 0) <= "101";
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wait for 75 ns;
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SW(2 downto 0) <= "010";
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wait for 19 ns;
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SW(2 downto 0) <= "111";
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wait for 100 ns;
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report "END OF SIMULATION" severity failure;
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end process;
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end architecture; |