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Joppe Blondel a9a33499a6 Fixed bugs in project.cfg for ghdl in formal 
Signed-off-by: Joppe Blondel <joppe@blondel.nl>
2022-09-06 13:15:47 +02:00
examples
Fixed bugs in project.cfg for ghdl in formal
2022-09-06 13:15:47 +02:00
remotesyn
Fixed bugs in project.cfg for ghdl in formal
2022-09-06 13:15:47 +02:00
scripts
Added remote continuous logging
2022-09-05 19:48:06 +02:00
.gitignore
Completed ISE impl
2022-09-04 20:07:45 +02:00
LICENCE
ISE coregen added
2022-09-05 13:55:03 +02:00
README.md
Squashed commit of the following:
2022-09-04 19:34:07 +02:00
setup.py
Squashed commit of the following:
2022-09-04 19:34:07 +02:00

README.md

The file is empty.
Description
Remote (ssh) FPGA synthesis abstraction tool which allows for remote and local synthesis. For Xilinx ISE and Vivado (and Intel Quartus comming soon)
Readme 1.6 MiB
Languages
Python 100%