16 lines
642 B
Tcl
16 lines
642 B
Tcl
create_ip -vlnv xilinx.com:ip:processing_system7 -module_name zynqps
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set_property -dict [ list \
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CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {16 Bit} \
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CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41K256M16 RE-125} \
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CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1} \
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CONFIG.PCW_UART1_UART1_IO {MIO 44 .. 45} \
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CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100} \
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CONFIG.PCW_USE_S_AXI_GP0 {0} \
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CONFIG.PCW_USE_M_AXI_GP0 {0} \
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CONFIG.PCW_USE_S_AXI_GP1 {0} \
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CONFIG.PCW_USE_M_AXI_GP1 {0} \
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CONFIG.PCW_USE_S_AXI_HP0 {0} \
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CONFIG.PCW_USE_S_AXI_HP1 {0} \
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CONFIG.PCW_USE_S_AXI_HP2 {0} \
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CONFIG.PCW_USE_S_AXI_HP3 {0} \
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] [ get_ips zynqps ] |