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Joppe Blondel 0e95f91fb2 Added isim target 
Signed-off-by: Joppe Blondel <joppe@blondel.nl>
2022-09-05 13:11:32 +02:00
examples/spartan6
Added isim target
2022-09-05 13:11:32 +02:00
remotesyn
Added isim target
2022-09-05 13:11:32 +02:00
scripts
Moved to more fusesoc like build style
2022-09-05 12:23:55 +02:00
.gitignore
Completed ISE impl
2022-09-04 20:07:45 +02:00
README.md
Squashed commit of the following:
2022-09-04 19:34:07 +02:00
setup.py
Squashed commit of the following:
2022-09-04 19:34:07 +02:00

README.md

The file is empty.
Description
Remote (ssh) FPGA synthesis abstraction tool which allows for remote and local synthesis. For Xilinx ISE and Vivado (and Intel Quartus comming soon)
Readme 1.6 MiB
Languages
Python 100%