19 lines
1.1 KiB
Markdown
19 lines
1.1 KiB
Markdown
# ZYNQ 7 series project
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### Basic FPGA workflow
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+ target `ip`: Generate IP blocks defined in the tcl files in the IP directory
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+ target `synth`: Synthesize design
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+ target `sim`: Behavioural simulation of part of the design
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+ target `psim`: Post synthesis simulation of mentioned part of the design
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### ZYNQ SoC workflos
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+ target `firmware`: Compile the firmware running on the ARM core(s) with the `make` toolchain
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+ target `firmsim`: Simulate the firmware with QEMU without PS/PL cosimulation with the `qemu` toolchain
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+ target `devtree`: Compile the device tree for a PS/PL cosimulation with QEMU
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+ target `cosim_ps`: PS part of the cosimulation. Must be ran first
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+ target `cosim_pl`: PL part of the cosimulation. Must be ran in a separate terminal while the PS part is still running
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### Notes:
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Compilation with Xilinx provided gcc and binutils done with `xsc` can be problematic... This is the reason
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Questasim is used for the cosimulation. If one would use the free Intel variant of Questasim post synthesis
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simulation will not be possible. The attempt to get DPI-C working with xsim is not stopped! |