joppe/remotesyn
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Added vivado synth

Browse Source 
Signed-off-by: Joppe Blondel <joppe@blondel.nl>
This commit is contained in:
Joppe Blondel
2022-09-05 15:08:27 +02:00
parent 15d072bbb7
commit b8267303a2
84 changed files with 212152 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

170
examples/.gen/sources_1/ip/zynqps/sim_tlm/b_transport_converter.h Executable file
View File

@ -0,0 +1,170 @@
// (c) Copyright(C) 2013 - 2018 by Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
#ifndef _B_TRANSPORT_CONVERTER_H_
#define _B_TRANSPORT_CONVERTER_H_
#include <systemc>
#include "tlm_utils/simple_target_socket.h"
#include "tlm_utils/simple_initiator_socket.h"
#include <utility>
#include <vector>
template<int IN_WIDTH, int OUT_WIDTH>
class b_transport_converter: public sc_core::sc_module
{
enum TLM_IF_TYPE
{
B_TRANSPORT = 0,
NB_TRANSPORT,
TRANSPORT_DBG,
DMI_IF,
INVALID_IF
};
typedef std::vector<std::pair<sc_dt::uint64, sc_dt::uint64>> addr_range_list;
public:
SC_HAS_PROCESS(b_transport_converter);
b_transport_converter<IN_WIDTH, OUT_WIDTH>(sc_core::sc_module_name name):
sc_module(name)
{
target_socket.register_b_transport(
this, &b_transport_converter<IN_WIDTH, OUT_WIDTH>::b_transport);
initiator_socket.register_nb_transport_bw(
this, &b_transport_converter<IN_WIDTH, OUT_WIDTH>::nb_transport_bw);
}
//simple tlm target/initiator socket...
tlm_utils::simple_target_socket<b_transport_converter<IN_WIDTH, OUT_WIDTH>, IN_WIDTH> target_socket;
tlm_utils::simple_initiator_socket<b_transport_converter<IN_WIDTH, OUT_WIDTH>, OUT_WIDTH> initiator_socket;
public:
void b_transport(tlm::tlm_generic_payload& payload, sc_core::sc_time& time)
{
tlm::tlm_phase phase = tlm::BEGIN_REQ; //for nb_transport_fw
switch(get_tlm_if_type(payload.get_address()))
{
case B_TRANSPORT:
initiator_socket->b_transport(payload, time);
break;
case NB_TRANSPORT:
initiator_socket->nb_transport_fw(payload, phase, time);
wait(resp_complete_event); //! Wait for the response to complete
break;
case TRANSPORT_DBG:
initiator_socket->transport_dbg(payload);
break;
case DMI_IF:
break;
default:
SC_REPORT_ERROR(this->name(), "Address not mapped to any of the TLM IF type");
}
}
tlm::tlm_sync_enum
nb_transport_bw(tlm::tlm_generic_payload& payload,
tlm::tlm_phase& phase, sc_core::sc_time& time)
{
if(phase == tlm::BEGIN_RESP) {
resp_complete_event.notify();
phase = tlm::END_RESP;
return tlm::TLM_UPDATED;
}
return tlm::TLM_ACCEPTED;
}
private:
TLM_IF_TYPE get_tlm_if_type(unsigned long long address)
{
//check for b_transport addresses
for(auto& addr_range: m_b_transport_addr_list) {
if(address >= addr_range.first && address < addr_range.second) {
return B_TRANSPORT;
}
}
//check for nb_transport addresses
for(auto& addr_range: m_nb_transport_addr_list) {
if(address >= addr_range.first && address < addr_range.second) {
return NB_TRANSPORT;
}
}
//check for dbg_transport addresses
for(auto& addr_range: m_dbg_transport_addr_list) {
if(address >= addr_range.first && address < addr_range.second) {
return TRANSPORT_DBG;
}
}
//By default return NB_TRANSPORT
return NB_TRANSPORT;
}
//Start and End Address List for each of interfaces...
static addr_range_list m_b_transport_addr_list;
static addr_range_list m_nb_transport_addr_list;
static addr_range_list m_dbg_transport_addr_list;
//event to notify completion of transaction
sc_core::sc_event resp_complete_event;
};
template<int IN_WIDTH, int OUT_WIDTH>
typename b_transport_converter<IN_WIDTH,OUT_WIDTH>::addr_range_list b_transport_converter<IN_WIDTH,OUT_WIDTH>::m_b_transport_addr_list = {std::make_pair(0, 0)};
template<int IN_WIDTH, int OUT_WIDTH>
typename b_transport_converter<IN_WIDTH,OUT_WIDTH>::addr_range_list b_transport_converter<IN_WIDTH,OUT_WIDTH>::m_nb_transport_addr_list = {std::make_pair(0, 0)};
template<int IN_WIDTH, int OUT_WIDTH>
typename b_transport_converter<IN_WIDTH,OUT_WIDTH>::addr_range_list b_transport_converter<IN_WIDTH,OUT_WIDTH>::m_dbg_transport_addr_list = {std::make_pair(0, 0)};
#endif /* _B_TRANSPORT_CONVERTER_H_ */

228
examples/.gen/sources_1/ip/zynqps/sim_tlm/processing_system7_v5_5_tlm.cpp Normal file
View File

@ -0,0 +1,228 @@
// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
#include"processing_system7_v5_5_tlm.h"
#include<string>
template <int IN_WIDTH, int OUT_WIDTH>
rptlm2xtlm_converter<IN_WIDTH, OUT_WIDTH>::rptlm2xtlm_converter(sc_module_name name):sc_module(name)
,target_socket("target_socket")
,wr_socket("init_wr_socket",OUT_WIDTH)
,rd_socket("init_rd_socket",OUT_WIDTH)
,m_btrans_conv("b_transport_converter")
,xtlm_bridge("tlm2xtlmbridge")
{
target_socket.bind(m_btrans_conv.target_socket);
m_btrans_conv.initiator_socket.bind(xtlm_bridge.target_socket);
xtlm_bridge.rd_socket->bind(rd_socket);
xtlm_bridge.wr_socket->bind(wr_socket);
}
template <int IN_WIDTH, int OUT_WIDTH>
void rptlm2xtlm_converter<IN_WIDTH, OUT_WIDTH>::registerUserExtensionHandlerCallback(
void (*callback)(xtlm::aximm_payload*,
const tlm::tlm_generic_payload*)) {
xtlm_bridge.registerUserExtensionHandlerCallback(callback);
}
/***************************************************************************************
* Global method, get registered with tlm2xtlm bridge
* This function is called when tlm2xtlm bridge convert tlm payload to xtlm payload.
*
* caller: tlm2xtlm bridge
* purpose: To get master id and other parameters out of genattr_extension
* and use master id to AxUSER PIN of xtlm payload.
*
*
***************************************************************************************/
void get_extensions_from_tlm(xtlm::aximm_payload* xtlm_pay, const tlm::tlm_generic_payload* gp)
{
if((xtlm_pay == NULL) || (gp == NULL))
return;
if((gp->get_command() == tlm::TLM_WRITE_COMMAND) && (xtlm_pay->get_awuser_size() > 0))
{
genattr_extension* ext = NULL;
gp->get_extension(ext);
if(ext == NULL)
return;
//Portion of master ID(master_id[5:0]) are transfered on AxUSER bits(refere Zynq UltraScale+ TRM page.no:414)
uint32_t val = ext->get_master_id() && 0x3F;
unsigned char* ptr = xtlm_pay->get_awuser_ptr();
unsigned int size = xtlm_pay->get_awuser_size();
*ptr = (unsigned char)val;
}
else if((gp->get_command() == tlm::TLM_READ_COMMAND) && (xtlm_pay->get_aruser_size() > 0))
{
genattr_extension* ext = NULL;
gp->get_extension(ext);
if(ext == NULL)
return;
//Portion of master ID(master_id[5:0]) are transfered on AxUSER bits(refere Zynq UltraScale+ TRM page.no:414)
uint32_t val = ext->get_master_id() && 0x3F;
unsigned char* ptr = xtlm_pay->get_aruser_ptr();
unsigned int size = xtlm_pay->get_aruser_size();
*ptr = (unsigned char)val;
}
}
/***************************************************************************************
* Global method, get registered with xtlm2tlm bridge
* This function is called when xtlm2tlm bridge convert xtlm payload to tlm payload.
*
* caller: xtlm2tlm bridge
* purpose: To create and add master id and other parameters to genattr_extension.
* Master id red from AxID PIN of xtlm payload.
*
*
***************************************************************************************/
void add_extensions_to_tlm(const xtlm::aximm_payload* xtlm_pay, tlm::tlm_generic_payload* gp)
{
if(gp == NULL)
return;
uint8_t val = 0;
if((gp->get_command() != tlm::TLM_WRITE_COMMAND) && (gp->get_command() != tlm::TLM_READ_COMMAND))
return;
//portion of master ID bits(master_id[5:0]) are derived from the AXI ID(AWID/ARID). (refere Zynq UltraScale+ TRM page.no:414,415)
//val = (*(uint8_t*)(xtlm_pay->get_axi_id())) && 0x3F;
genattr_extension* ext = new genattr_extension;
ext->set_master_id(val);
gp->set_extension(ext);
gp->set_streaming_width(gp->get_data_length());
if(gp->get_command() != tlm::TLM_WRITE_COMMAND)
{
gp->set_byte_enable_length(0);
gp->set_byte_enable_ptr(0);
}
}
processing_system7_v5_5_tlm :: processing_system7_v5_5_tlm (sc_core::sc_module_name name,
xsc::common_cpp::properties& _prop): sc_module(name)//registering module name with parent
,FCLK_CLK0("FCLK_CLK0")
,FCLK_RESET0_N("FCLK_RESET0_N")
,MIO("MIO")
,DDR_CAS_n("DDR_CAS_n")
,DDR_CKE("DDR_CKE")
,DDR_Clk_n("DDR_Clk_n")
,DDR_Clk("DDR_Clk")
,DDR_CS_n("DDR_CS_n")
,DDR_DRSTB("DDR_DRSTB")
,DDR_ODT("DDR_ODT")
,DDR_RAS_n("DDR_RAS_n")
,DDR_WEB("DDR_WEB")
,DDR_BankAddr("DDR_BankAddr")
,DDR_Addr("DDR_Addr")
,DDR_VRN("DDR_VRN")
,DDR_VRP("DDR_VRP")
,DDR_DM("DDR_DM")
,DDR_DQ("DDR_DQ")
,DDR_DQS_n("DDR_DQS_n")
,DDR_DQS("DDR_DQS")
,PS_SRSTB("PS_SRSTB")
,PS_CLK("PS_CLK")
,PS_PORB("PS_PORB")
,FCLK_CLK0_clk("FCLK_CLK0_clk", sc_time(10000.0,sc_core::SC_PS))//clock period in picoseconds = 1000000/freq(in MZ)
,prop(_prop)
{
//creating instances of xtlm slave sockets
//creating instances of xtlm master sockets
char* unix_path = getenv("COSIM_MACHINE_PATH");
char* tcpip_addr = getenv("COSIM_MACHINE_TCPIP_ADDRESS");
char* dir_path_to_test_machine;
bool unix_socket_en = false;
if (unix_path != nullptr) {
dir_path_to_test_machine = strdup(unix_path);
unix_socket_en = true;
}
if ((unix_socket_en == false) && (tcpip_addr != nullptr)) {
dir_path_to_test_machine = strdup(tcpip_addr);
} else if (unix_socket_en == false) {
printf(
"ERROR: Environment Variables Either COSIM_MACHINE_TCPIP_ADDRESS or COSIM_MACHINE_PATH is not specified.\n 1. Specify COSIM_MACHINE_PATH for Unix Socket Communication.\n 2. Specify COSIM_MACHINE_TCPIP_ADDRESS for TCP Socket Communication.\n");
exit(0);
}
std::string skt_name;
if (unix_socket_en) {
skt_name.append("unix:");
skt_name.append(dir_path_to_test_machine);
skt_name.append("//qemu-rport-_cosim@0");
} else {
skt_name.append(dir_path_to_test_machine);
}
const char* skt = skt_name.c_str();
m_zynq_tlm_model = new xilinx_zynq("xilinx_zynq",skt);
m_zynq_tlm_model->tie_off();
SC_METHOD(trigger_FCLK_CLK0_pin);
sensitive << FCLK_CLK0_clk;
dont_initialize();
m_zynq_tlm_model->rst(qemu_rst);
}
processing_system7_v5_5_tlm :: ~processing_system7_v5_5_tlm() {
//deleteing dynamically created objects
}
//Method which is sentive to FCLK_CLK0_clk sc_clock object
//FCLK_CLK0 pin written based on FCLK_CLK0_clk clock value
void processing_system7_v5_5_tlm ::trigger_FCLK_CLK0_pin() {
FCLK_CLK0.write(FCLK_CLK0_clk.read());
}
//ps2pl_rst[0] output reset pin
void processing_system7_v5_5_tlm :: FCLK_RESET0_N_trigger() {
FCLK_RESET0_N.write(m_zynq_tlm_model->ps2pl_rst[0].read());
}
void processing_system7_v5_5_tlm ::start_of_simulation()
{
//temporary fix to drive the enabled reset pin
FCLK_RESET0_N.write(true);
qemu_rst.write(false);
}

212
examples/.gen/sources_1/ip/zynqps/sim_tlm/processing_system7_v5_5_tlm.h Normal file
View File

@ -0,0 +1,212 @@
// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:processing_system7_vip:1.0
// IP Revision: 1
#ifndef __PS7_H__
#define __PS7_H__
#include "systemc.h"
#include "xtlm.h"
#include "xtlm_adaptors/xaximm_xtlm2tlm.h"
#include "xtlm_adaptors/xaximm_tlm2xtlm.h"
#include "tlm_utils/simple_initiator_socket.h"
#include "tlm_utils/simple_target_socket.h"
#include "genattr.h"
#include "xilinx-zynq.h"
#include "b_transport_converter.h"
#include "utils/xtlm_aximm_fifo.h"
/***************************************************************************************
*
* A Simple Converter which converts Remote-port's simplae_intiator_sockets<32>->b_transport()
* calls to xTLM sockets bn_transport_x() calls..
*
* This is Only specific to remote-port so not creating seperate header for it.
*
***************************************************************************************/
template <int IN_WIDTH, int OUT_WIDTH>
class rptlm2xtlm_converter : public sc_module{
public:
tlm::tlm_target_socket<IN_WIDTH> target_socket;
xtlm::xtlm_aximm_initiator_socket wr_socket;
xtlm::xtlm_aximm_initiator_socket rd_socket;
rptlm2xtlm_converter<IN_WIDTH, OUT_WIDTH>(sc_module_name name);//:sc_module(name)
void registerUserExtensionHandlerCallback(
void (*callback)(xtlm::aximm_payload*,
const tlm::tlm_generic_payload*));
private:
b_transport_converter<IN_WIDTH, OUT_WIDTH> m_btrans_conv;
xtlm::xaximm_tlm2xtlm_t<OUT_WIDTH> xtlm_bridge;
};
/***************************************************************************************
* Global method, get registered with tlm2xtlm bridge
* This function is called when tlm2xtlm bridge convert tlm payload to xtlm payload.
*
* caller: tlm2xtlm bridge
* purpose: To get master id and other parameters out of genattr_extension
* and use master id to AxUSER PIN of xtlm payload.
*
*
***************************************************************************************/
extern void get_extensions_from_tlm(xtlm::aximm_payload* xtlm_pay, const tlm::tlm_generic_payload* gp);
/***************************************************************************************
* Global method, get registered with xtlm2tlm bridge
* This function is called when xtlm2tlm bridge convert xtlm payload to tlm payload.
*
* caller: xtlm2tlm bridge
* purpose: To create and add master id and other parameters to genattr_extension.
* Master id red from AxID PIN of xtlm payload.
*
*
***************************************************************************************/
extern void add_extensions_to_tlm(const xtlm::aximm_payload* xtlm_pay, tlm::tlm_generic_payload* gp);
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// //
// File: processing_system7_tlm.h //
// //
// Description: zynq_ultra_ps_e_tlm class is a sc_module, act as intermediate layer between //
// xilinx_zynq qemu wrapper and Vivado generated systemc simulation ip wrapper. //
// it's basically created for supporting tlm based xilinx_zynq from xtlm based vivado //
// generated systemc wrapper. this wrapper is live only when SELECTED_SIM_MODEL is set //
// to tlm. it's also act as bridge between vivado wrapper and xilinx_zynq wrapper. //
// it fill the the gap between input/output ports of vivado generated wrapper to //
// xilinx_zynq wrapper signals. This wrapper is auto generated by ttcl scripts //
// based on IP configuration in vivado. //
// //
// //
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
class processing_system7_v5_5_tlm : public sc_core::sc_module {
public:
// Non-AXI ports are declared here
sc_core::sc_out<bool> FCLK_CLK0;
sc_core::sc_out<bool> FCLK_RESET0_N;
sc_core::sc_inout<sc_dt::sc_bv<54> > MIO;
sc_core::sc_inout<bool> DDR_CAS_n;
sc_core::sc_inout<bool> DDR_CKE;
sc_core::sc_inout<bool> DDR_Clk_n;
sc_core::sc_inout<bool> DDR_Clk;
sc_core::sc_inout<bool> DDR_CS_n;
sc_core::sc_inout<bool> DDR_DRSTB;
sc_core::sc_inout<bool> DDR_ODT;
sc_core::sc_inout<bool> DDR_RAS_n;
sc_core::sc_inout<bool> DDR_WEB;
sc_core::sc_inout<sc_dt::sc_bv<3> > DDR_BankAddr;
sc_core::sc_inout<sc_dt::sc_bv<15> > DDR_Addr;
sc_core::sc_inout<bool> DDR_VRN;
sc_core::sc_inout<bool> DDR_VRP;
sc_core::sc_inout<sc_dt::sc_bv<4> > DDR_DM;
sc_core::sc_inout<sc_dt::sc_bv<32> > DDR_DQ;
sc_core::sc_inout<sc_dt::sc_bv<4> > DDR_DQS_n;
sc_core::sc_inout<sc_dt::sc_bv<4> > DDR_DQS;
sc_core::sc_inout<bool> PS_SRSTB;
sc_core::sc_inout<bool> PS_CLK;
sc_core::sc_inout<bool> PS_PORB;
//constructor having three paramters
// 1. module name in sc_module_name objec,
// 2. reference to map object of name and integer value pairs
// 3. reference to map object of name and string value pairs
// All the model parameters (integer and string) which are configuration parameters
// of Processing System 7 IP propogated from Vivado
processing_system7_v5_5_tlm(sc_core::sc_module_name name,
xsc::common_cpp::properties&);
~processing_system7_v5_5_tlm();
SC_HAS_PROCESS(processing_system7_v5_5_tlm);
private:
//zynq tlm wrapper provided by Edgar
//module with interfaces of standard tlm
//and input/output ports at signal level
xilinx_zynq* m_zynq_tlm_model;
// Xtlm2tlm_t Bridges
// Converts Xtlm transactions to tlm transactions
// Bridge's Xtlm wr/rd target sockets binds with
// xtlm initiator sockets of processing_system7_tlm and tlm simple initiator
// socket with xilinx_zynq's target socket
// This Bridges converts b_transport to nb_transports and also
// Converts tlm transactions to xtlm transactions.
// Bridge's tlm simple target socket binds with
// simple initiator socket of xilinx_zynqmp and xtlm
// socket with xilinx_zynq's simple target socket
// sc_clocks for generating pl clocks
// output pins FCLK_CLK0..3 are drived by these clocks
sc_core::sc_clock FCLK_CLK0_clk;
//Method which is sentive to FCLK_CLK0_clk sc_clock object
//FCLK_CLK0 pin written based on FCLK_CLK0_clk clock value
void trigger_FCLK_CLK0_pin();
//FCLK_RESET0 output reset pin get toggle when emio bank 2's 31th signal gets toggled
//EMIO[2] bank 31th(GPIO[95] signal)acts as reset signal to the PL(refer Zynq UltraScale+ TRM, page no:761)
void FCLK_RESET0_N_trigger();
sc_signal<bool> qemu_rst;
void start_of_simulation();
xsc::common_cpp::properties prop;
};
#endif

106
examples/.gen/sources_1/ip/zynqps/sim_tlm/xilinx-zynq.cc Executable file
View File

@ -0,0 +1,106 @@
/*
* Xilinx SystemC/TLM-2.0 Zynq Wrapper.
*
* Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
*
* Copyright (c) 2016, Xilinx Inc.
* All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#define SC_INCLUDE_DYNAMIC_PROCESSES
#include <inttypes.h>
#include "tlm_utils/simple_initiator_socket.h"
#include "tlm_utils/simple_target_socket.h"
using namespace sc_core;
using namespace std;
#include "xilinx-zynq.h"
#include <sys/types.h>
//xilinx_zynq::xilinx_zynq(sc_module_name name, const char *sk_descr,
// Iremoteport_tlm_sync *sync)
// : remoteport_tlm(name, -1, sk_descr, sync),
xilinx_zynq::xilinx_zynq(sc_module_name name, const char *sk_descr)
: remoteport_tlm(name, -1, sk_descr),
rp_m_axi_gp0("rp_m_axi_gp0"),
rp_m_axi_gp1("rp_m_axi_gp1"),
rp_s_axi_gp0("rp_s_axi_gp0"),
rp_s_axi_gp1("rp_s_axi_gp1"),
rp_s_axi_hp0("rp_s_axi_hp0"),
rp_s_axi_hp1("rp_s_axi_hp1"),
rp_s_axi_hp2("rp_s_axi_hp2"),
rp_s_axi_hp3("rp_s_axi_hp3"),
rp_s_axi_acp("rp_s_axi_acp"),
rp_wires_in("wires_in", 20, 0),
rp_wires_out("wires_out", 0, 17),
rp_irq_out("irq_out", 0, 28),
pl2ps_irq("pl2ps_irq", 20),
ps2pl_irq("ps2pl_irq", 28),
ps2pl_rst("ps2pl_rst", 17)
{
int i;
m_axi_gp[0] = &rp_m_axi_gp0.sk;
m_axi_gp[1] = &rp_m_axi_gp1.sk;
s_axi_gp[0] = &rp_s_axi_gp0.sk;
s_axi_gp[1] = &rp_s_axi_gp1.sk;
s_axi_hp[0] = &rp_s_axi_hp0.sk;
s_axi_hp[1] = &rp_s_axi_hp1.sk;
s_axi_hp[2] = &rp_s_axi_hp2.sk;
s_axi_hp[3] = &rp_s_axi_hp3.sk;
s_axi_acp = &rp_s_axi_acp.sk;
/* PL to PS Interrupt signals. */
for (i = 0; i < 20; i++) {
rp_wires_in.wires_in[i](pl2ps_irq[i]);
}
/* PS to PL Interrupt signals. */
for (i = 0; i < 28; i++) {
rp_irq_out.wires_out[i](ps2pl_irq[i]);
}
/* PS to PL resets. */
for (i = 0; i < 17; i++) {
rp_wires_out.wires_out[i](ps2pl_rst[i]);
}
register_dev(0, &rp_s_axi_gp0);
register_dev(1, &rp_s_axi_gp1);
register_dev(2, &rp_s_axi_hp0);
register_dev(3, &rp_s_axi_hp1);
register_dev(4, &rp_s_axi_hp2);
register_dev(5, &rp_s_axi_hp3);
register_dev(6, &rp_s_axi_acp);
register_dev(7, &rp_m_axi_gp0);
register_dev(8, &rp_m_axi_gp1);
register_dev(9, &rp_wires_in);
register_dev(10, &rp_wires_out);
register_dev(11, &rp_irq_out);
}

104
examples/.gen/sources_1/ip/zynqps/sim_tlm/xilinx-zynq.h Executable file
View File

@ -0,0 +1,104 @@
/*
* Xilinx SystemC/TLM-2.0 Zynq Wrapper.
*
* Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
*
* Copyright (c) 2016, Xilinx Inc.
* All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include "systemc.h"
#include "tlm_utils/simple_initiator_socket.h"
#include "tlm_utils/simple_target_socket.h"
#include "tlm_utils/tlm_quantumkeeper.h"
#include "remote-port-tlm.h"
#include "remote-port-tlm-memory-master.h"
#include "remote-port-tlm-memory-slave.h"
#include "remote-port-tlm-wires.h"
class xilinx_zynq
: public remoteport_tlm
{
private:
remoteport_tlm_memory_master rp_m_axi_gp0;
remoteport_tlm_memory_master rp_m_axi_gp1;
remoteport_tlm_memory_slave rp_s_axi_gp0;
remoteport_tlm_memory_slave rp_s_axi_gp1;
remoteport_tlm_memory_slave rp_s_axi_hp0;
remoteport_tlm_memory_slave rp_s_axi_hp1;
remoteport_tlm_memory_slave rp_s_axi_hp2;
remoteport_tlm_memory_slave rp_s_axi_hp3;
remoteport_tlm_memory_slave rp_s_axi_acp;
remoteport_tlm_wires rp_wires_in;
remoteport_tlm_wires rp_wires_out;
remoteport_tlm_wires rp_irq_out;
public:
/*
* M_AXI_GP 0 - 1.
* These sockets represent the High speed PS to PL interfaces.
* These are AXI Slave ports on the PS side and AXI Master ports
* on the PL side.
*
* Used to transfer data from the PS to the PL.
*/
tlm_utils::simple_initiator_socket<remoteport_tlm_memory_master> *m_axi_gp[2];
/*
* S_AXI_GP0 - 1.
* These sockets represent the High speed IO Coherent PL to PS
* interfaces.
*
* HP0 - 3.
* These sockets represent the High performance dataflow PL to PS interfaces.
*
* ACP
* Accelerator Coherency Port, used to transfered coherent data to
* the PS via the Cortex-A9 subsystem.
*
* These are AXI Master ports on the PS side and AXI Slave ports
* on the PL side.
*
* Used to transfer data from the PL to the PS.
*/
tlm_utils::simple_target_socket<remoteport_tlm_memory_slave> *s_axi_gp[2];
tlm_utils::simple_target_socket<remoteport_tlm_memory_slave> *s_axi_hp[4];
tlm_utils::simple_target_socket<remoteport_tlm_memory_slave> *s_axi_acp;
/* PL (fabric) to PS interrupt signals. */
sc_vector<sc_signal<bool> > pl2ps_irq;
/* PS to PL Interrupt signals. */
sc_vector<sc_signal<bool> > ps2pl_irq;
/* FPGA out resets. */
sc_vector<sc_signal<bool> > ps2pl_rst;
xilinx_zynq(sc_core::sc_module_name name, const char *sk_descr);
//xilinx_zynq(sc_core::sc_module_name name, const char *sk_descr,
// Iremoteport_tlm_sync *sync = NULL);
};