107 lines
3.2 KiB
C++
Executable File
107 lines
3.2 KiB
C++
Executable File
/*
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* Xilinx SystemC/TLM-2.0 Zynq Wrapper.
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*
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* Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
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*
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* Copyright (c) 2016, Xilinx Inc.
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* All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#define SC_INCLUDE_DYNAMIC_PROCESSES
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#include <inttypes.h>
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#include "tlm_utils/simple_initiator_socket.h"
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#include "tlm_utils/simple_target_socket.h"
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using namespace sc_core;
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using namespace std;
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#include "xilinx-zynq.h"
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#include <sys/types.h>
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//xilinx_zynq::xilinx_zynq(sc_module_name name, const char *sk_descr,
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// Iremoteport_tlm_sync *sync)
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// : remoteport_tlm(name, -1, sk_descr, sync),
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xilinx_zynq::xilinx_zynq(sc_module_name name, const char *sk_descr)
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: remoteport_tlm(name, -1, sk_descr),
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rp_m_axi_gp0("rp_m_axi_gp0"),
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rp_m_axi_gp1("rp_m_axi_gp1"),
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rp_s_axi_gp0("rp_s_axi_gp0"),
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rp_s_axi_gp1("rp_s_axi_gp1"),
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rp_s_axi_hp0("rp_s_axi_hp0"),
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rp_s_axi_hp1("rp_s_axi_hp1"),
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rp_s_axi_hp2("rp_s_axi_hp2"),
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rp_s_axi_hp3("rp_s_axi_hp3"),
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rp_s_axi_acp("rp_s_axi_acp"),
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rp_wires_in("wires_in", 20, 0),
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rp_wires_out("wires_out", 0, 17),
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rp_irq_out("irq_out", 0, 28),
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pl2ps_irq("pl2ps_irq", 20),
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ps2pl_irq("ps2pl_irq", 28),
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ps2pl_rst("ps2pl_rst", 17)
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{
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int i;
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m_axi_gp[0] = &rp_m_axi_gp0.sk;
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m_axi_gp[1] = &rp_m_axi_gp1.sk;
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s_axi_gp[0] = &rp_s_axi_gp0.sk;
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s_axi_gp[1] = &rp_s_axi_gp1.sk;
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s_axi_hp[0] = &rp_s_axi_hp0.sk;
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s_axi_hp[1] = &rp_s_axi_hp1.sk;
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s_axi_hp[2] = &rp_s_axi_hp2.sk;
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s_axi_hp[3] = &rp_s_axi_hp3.sk;
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s_axi_acp = &rp_s_axi_acp.sk;
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/* PL to PS Interrupt signals. */
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for (i = 0; i < 20; i++) {
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rp_wires_in.wires_in[i](pl2ps_irq[i]);
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}
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/* PS to PL Interrupt signals. */
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for (i = 0; i < 28; i++) {
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rp_irq_out.wires_out[i](ps2pl_irq[i]);
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}
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/* PS to PL resets. */
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for (i = 0; i < 17; i++) {
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rp_wires_out.wires_out[i](ps2pl_rst[i]);
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}
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register_dev(0, &rp_s_axi_gp0);
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register_dev(1, &rp_s_axi_gp1);
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register_dev(2, &rp_s_axi_hp0);
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register_dev(3, &rp_s_axi_hp1);
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register_dev(4, &rp_s_axi_hp2);
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register_dev(5, &rp_s_axi_hp3);
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register_dev(6, &rp_s_axi_acp);
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register_dev(7, &rp_m_axi_gp0);
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register_dev(8, &rp_m_axi_gp1);
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register_dev(9, &rp_wires_in);
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register_dev(10, &rp_wires_out);
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register_dev(11, &rp_irq_out);
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}
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