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Added vivado synth

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Signed-off-by: Joppe Blondel <joppe@blondel.nl>
This commit is contained in:
Joppe Blondel
2022-09-05 15:08:27 +02:00
parent 15d072bbb7
commit b8267303a2
84 changed files with 212152 additions and 2 deletions
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examples/.gen/sources_1/ip/zynqps/sim/libps7.dll Executable file
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// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.

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examples/.gen/sources_1/ip/zynqps/sim/libps7.so Executable file
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// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.

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examples/.gen/sources_1/ip/zynqps/sim/libremoteport.dll Executable file
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// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.

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examples/.gen/sources_1/ip/zynqps/sim/libremoteport.so Executable file
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// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.

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examples/.gen/sources_1/ip/zynqps/sim/zynqps.cpp Normal file
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// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
#include "zynqps_sc.h"
#include "zynqps.h"
#include "processing_system7_v5_5_tlm.h"
#include <map>
#include <string>
#ifdef XILINX_SIMULATOR
zynqps::zynqps(const sc_core::sc_module_name& nm) : zynqps_sc(nm), FCLK_CLK0("FCLK_CLK0"), FCLK_RESET0_N("FCLK_RESET0_N"), MIO("MIO"), DDR_CAS_n("DDR_CAS_n"), DDR_CKE("DDR_CKE"), DDR_Clk_n("DDR_Clk_n"), DDR_Clk("DDR_Clk"), DDR_CS_n("DDR_CS_n"), DDR_DRSTB("DDR_DRSTB"), DDR_ODT("DDR_ODT"), DDR_RAS_n("DDR_RAS_n"), DDR_WEB("DDR_WEB"), DDR_BankAddr("DDR_BankAddr"), DDR_Addr("DDR_Addr"), DDR_VRN("DDR_VRN"), DDR_VRP("DDR_VRP"), DDR_DM("DDR_DM"), DDR_DQ("DDR_DQ"), DDR_DQS_n("DDR_DQS_n"), DDR_DQS("DDR_DQS"), PS_SRSTB("PS_SRSTB"), PS_CLK("PS_CLK"), PS_PORB("PS_PORB")
{
// initialize pins
mp_impl->FCLK_CLK0(FCLK_CLK0);
mp_impl->FCLK_RESET0_N(FCLK_RESET0_N);
mp_impl->MIO(MIO);
mp_impl->DDR_CAS_n(DDR_CAS_n);
mp_impl->DDR_CKE(DDR_CKE);
mp_impl->DDR_Clk_n(DDR_Clk_n);
mp_impl->DDR_Clk(DDR_Clk);
mp_impl->DDR_CS_n(DDR_CS_n);
mp_impl->DDR_DRSTB(DDR_DRSTB);
mp_impl->DDR_ODT(DDR_ODT);
mp_impl->DDR_RAS_n(DDR_RAS_n);
mp_impl->DDR_WEB(DDR_WEB);
mp_impl->DDR_BankAddr(DDR_BankAddr);
mp_impl->DDR_Addr(DDR_Addr);
mp_impl->DDR_VRN(DDR_VRN);
mp_impl->DDR_VRP(DDR_VRP);
mp_impl->DDR_DM(DDR_DM);
mp_impl->DDR_DQ(DDR_DQ);
mp_impl->DDR_DQS_n(DDR_DQS_n);
mp_impl->DDR_DQS(DDR_DQS);
mp_impl->PS_SRSTB(PS_SRSTB);
mp_impl->PS_CLK(PS_CLK);
mp_impl->PS_PORB(PS_PORB);
}
void zynqps::before_end_of_elaboration()
{
}
#endif // XILINX_SIMULATOR
#ifdef XM_SYSTEMC
zynqps::zynqps(const sc_core::sc_module_name& nm) : zynqps_sc(nm), FCLK_CLK0("FCLK_CLK0"), FCLK_RESET0_N("FCLK_RESET0_N"), MIO("MIO"), DDR_CAS_n("DDR_CAS_n"), DDR_CKE("DDR_CKE"), DDR_Clk_n("DDR_Clk_n"), DDR_Clk("DDR_Clk"), DDR_CS_n("DDR_CS_n"), DDR_DRSTB("DDR_DRSTB"), DDR_ODT("DDR_ODT"), DDR_RAS_n("DDR_RAS_n"), DDR_WEB("DDR_WEB"), DDR_BankAddr("DDR_BankAddr"), DDR_Addr("DDR_Addr"), DDR_VRN("DDR_VRN"), DDR_VRP("DDR_VRP"), DDR_DM("DDR_DM"), DDR_DQ("DDR_DQ"), DDR_DQS_n("DDR_DQS_n"), DDR_DQS("DDR_DQS"), PS_SRSTB("PS_SRSTB"), PS_CLK("PS_CLK"), PS_PORB("PS_PORB")
{
// initialize pins
mp_impl->FCLK_CLK0(FCLK_CLK0);
mp_impl->FCLK_RESET0_N(FCLK_RESET0_N);
mp_impl->MIO(MIO);
mp_impl->DDR_CAS_n(DDR_CAS_n);
mp_impl->DDR_CKE(DDR_CKE);
mp_impl->DDR_Clk_n(DDR_Clk_n);
mp_impl->DDR_Clk(DDR_Clk);
mp_impl->DDR_CS_n(DDR_CS_n);
mp_impl->DDR_DRSTB(DDR_DRSTB);
mp_impl->DDR_ODT(DDR_ODT);
mp_impl->DDR_RAS_n(DDR_RAS_n);
mp_impl->DDR_WEB(DDR_WEB);
mp_impl->DDR_BankAddr(DDR_BankAddr);
mp_impl->DDR_Addr(DDR_Addr);
mp_impl->DDR_VRN(DDR_VRN);
mp_impl->DDR_VRP(DDR_VRP);
mp_impl->DDR_DM(DDR_DM);
mp_impl->DDR_DQ(DDR_DQ);
mp_impl->DDR_DQS_n(DDR_DQS_n);
mp_impl->DDR_DQS(DDR_DQS);
mp_impl->PS_SRSTB(PS_SRSTB);
mp_impl->PS_CLK(PS_CLK);
mp_impl->PS_PORB(PS_PORB);
}
void zynqps::before_end_of_elaboration()
{
}
#endif // XM_SYSTEMC
#ifdef RIVIERA
zynqps::zynqps(const sc_core::sc_module_name& nm) : zynqps_sc(nm), FCLK_CLK0("FCLK_CLK0"), FCLK_RESET0_N("FCLK_RESET0_N"), MIO("MIO"), DDR_CAS_n("DDR_CAS_n"), DDR_CKE("DDR_CKE"), DDR_Clk_n("DDR_Clk_n"), DDR_Clk("DDR_Clk"), DDR_CS_n("DDR_CS_n"), DDR_DRSTB("DDR_DRSTB"), DDR_ODT("DDR_ODT"), DDR_RAS_n("DDR_RAS_n"), DDR_WEB("DDR_WEB"), DDR_BankAddr("DDR_BankAddr"), DDR_Addr("DDR_Addr"), DDR_VRN("DDR_VRN"), DDR_VRP("DDR_VRP"), DDR_DM("DDR_DM"), DDR_DQ("DDR_DQ"), DDR_DQS_n("DDR_DQS_n"), DDR_DQS("DDR_DQS"), PS_SRSTB("PS_SRSTB"), PS_CLK("PS_CLK"), PS_PORB("PS_PORB")
{
// initialize pins
mp_impl->FCLK_CLK0(FCLK_CLK0);
mp_impl->FCLK_RESET0_N(FCLK_RESET0_N);
mp_impl->MIO(MIO);
mp_impl->DDR_CAS_n(DDR_CAS_n);
mp_impl->DDR_CKE(DDR_CKE);
mp_impl->DDR_Clk_n(DDR_Clk_n);
mp_impl->DDR_Clk(DDR_Clk);
mp_impl->DDR_CS_n(DDR_CS_n);
mp_impl->DDR_DRSTB(DDR_DRSTB);
mp_impl->DDR_ODT(DDR_ODT);
mp_impl->DDR_RAS_n(DDR_RAS_n);
mp_impl->DDR_WEB(DDR_WEB);
mp_impl->DDR_BankAddr(DDR_BankAddr);
mp_impl->DDR_Addr(DDR_Addr);
mp_impl->DDR_VRN(DDR_VRN);
mp_impl->DDR_VRP(DDR_VRP);
mp_impl->DDR_DM(DDR_DM);
mp_impl->DDR_DQ(DDR_DQ);
mp_impl->DDR_DQS_n(DDR_DQS_n);
mp_impl->DDR_DQS(DDR_DQS);
mp_impl->PS_SRSTB(PS_SRSTB);
mp_impl->PS_CLK(PS_CLK);
mp_impl->PS_PORB(PS_PORB);
}
void zynqps::before_end_of_elaboration()
{
}
#endif // RIVIERA
#ifdef VCSSYSTEMC
zynqps::zynqps(const sc_core::sc_module_name& nm) : zynqps_sc(nm), FCLK_CLK0("FCLK_CLK0"), FCLK_RESET0_N("FCLK_RESET0_N"), MIO("MIO"), DDR_CAS_n("DDR_CAS_n"), DDR_CKE("DDR_CKE"), DDR_Clk_n("DDR_Clk_n"), DDR_Clk("DDR_Clk"), DDR_CS_n("DDR_CS_n"), DDR_DRSTB("DDR_DRSTB"), DDR_ODT("DDR_ODT"), DDR_RAS_n("DDR_RAS_n"), DDR_WEB("DDR_WEB"), DDR_BankAddr("DDR_BankAddr"), DDR_Addr("DDR_Addr"), DDR_VRN("DDR_VRN"), DDR_VRP("DDR_VRP"), DDR_DM("DDR_DM"), DDR_DQ("DDR_DQ"), DDR_DQS_n("DDR_DQS_n"), DDR_DQS("DDR_DQS"), PS_SRSTB("PS_SRSTB"), PS_CLK("PS_CLK"), PS_PORB("PS_PORB")
{
// initialize pins
mp_impl->FCLK_CLK0(FCLK_CLK0);
mp_impl->FCLK_RESET0_N(FCLK_RESET0_N);
mp_impl->MIO(MIO);
mp_impl->DDR_CAS_n(DDR_CAS_n);
mp_impl->DDR_CKE(DDR_CKE);
mp_impl->DDR_Clk_n(DDR_Clk_n);
mp_impl->DDR_Clk(DDR_Clk);
mp_impl->DDR_CS_n(DDR_CS_n);
mp_impl->DDR_DRSTB(DDR_DRSTB);
mp_impl->DDR_ODT(DDR_ODT);
mp_impl->DDR_RAS_n(DDR_RAS_n);
mp_impl->DDR_WEB(DDR_WEB);
mp_impl->DDR_BankAddr(DDR_BankAddr);
mp_impl->DDR_Addr(DDR_Addr);
mp_impl->DDR_VRN(DDR_VRN);
mp_impl->DDR_VRP(DDR_VRP);
mp_impl->DDR_DM(DDR_DM);
mp_impl->DDR_DQ(DDR_DQ);
mp_impl->DDR_DQS_n(DDR_DQS_n);
mp_impl->DDR_DQS(DDR_DQS);
mp_impl->PS_SRSTB(PS_SRSTB);
mp_impl->PS_CLK(PS_CLK);
mp_impl->PS_PORB(PS_PORB);
// Instantiate Socket Stubs
}
void zynqps::before_end_of_elaboration()
{
}
#endif // VCSSYSTEMC
#ifdef MTI_SYSTEMC
zynqps::zynqps(const sc_core::sc_module_name& nm) : zynqps_sc(nm), FCLK_CLK0("FCLK_CLK0"), FCLK_RESET0_N("FCLK_RESET0_N"), MIO("MIO"), DDR_CAS_n("DDR_CAS_n"), DDR_CKE("DDR_CKE"), DDR_Clk_n("DDR_Clk_n"), DDR_Clk("DDR_Clk"), DDR_CS_n("DDR_CS_n"), DDR_DRSTB("DDR_DRSTB"), DDR_ODT("DDR_ODT"), DDR_RAS_n("DDR_RAS_n"), DDR_WEB("DDR_WEB"), DDR_BankAddr("DDR_BankAddr"), DDR_Addr("DDR_Addr"), DDR_VRN("DDR_VRN"), DDR_VRP("DDR_VRP"), DDR_DM("DDR_DM"), DDR_DQ("DDR_DQ"), DDR_DQS_n("DDR_DQS_n"), DDR_DQS("DDR_DQS"), PS_SRSTB("PS_SRSTB"), PS_CLK("PS_CLK"), PS_PORB("PS_PORB")
{
// initialize pins
mp_impl->FCLK_CLK0(FCLK_CLK0);
mp_impl->FCLK_RESET0_N(FCLK_RESET0_N);
mp_impl->MIO(MIO);
mp_impl->DDR_CAS_n(DDR_CAS_n);
mp_impl->DDR_CKE(DDR_CKE);
mp_impl->DDR_Clk_n(DDR_Clk_n);
mp_impl->DDR_Clk(DDR_Clk);
mp_impl->DDR_CS_n(DDR_CS_n);
mp_impl->DDR_DRSTB(DDR_DRSTB);
mp_impl->DDR_ODT(DDR_ODT);
mp_impl->DDR_RAS_n(DDR_RAS_n);
mp_impl->DDR_WEB(DDR_WEB);
mp_impl->DDR_BankAddr(DDR_BankAddr);
mp_impl->DDR_Addr(DDR_Addr);
mp_impl->DDR_VRN(DDR_VRN);
mp_impl->DDR_VRP(DDR_VRP);
mp_impl->DDR_DM(DDR_DM);
mp_impl->DDR_DQ(DDR_DQ);
mp_impl->DDR_DQS_n(DDR_DQS_n);
mp_impl->DDR_DQS(DDR_DQS);
mp_impl->PS_SRSTB(PS_SRSTB);
mp_impl->PS_CLK(PS_CLK);
mp_impl->PS_PORB(PS_PORB);
// Instantiate Socket Stubs
}
void zynqps::before_end_of_elaboration()
{
}
#endif // MTI_SYSTEMC
zynqps::~zynqps()
{
}
#ifdef MTI_SYSTEMC
SC_MODULE_EXPORT(zynqps);
#endif
#ifdef XM_SYSTEMC
XMSC_MODULE_EXPORT(zynqps);
#endif
#ifdef RIVIERA
SC_MODULE_EXPORT(zynqps);
SC_REGISTER_BV(54);
#endif

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#ifndef IP_ZYNQPS_H_
#define IP_ZYNQPS_H_
// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
#ifndef XTLM
#include "xtlm.h"
#endif
#ifndef SYSTEMC_INCLUDED
#include <systemc>
#endif
#if defined(_MSC_VER)
#define DllExport __declspec(dllexport)
#elif defined(__GNUC__)
#define DllExport __attribute__ ((visibility("default")))
#else
#define DllExport
#endif
#include "zynqps_sc.h"
#ifdef XILINX_SIMULATOR
class DllExport zynqps : public zynqps_sc
{
public:
zynqps(const sc_core::sc_module_name& nm);
virtual ~zynqps();
// module pin-to-pin RTL interface
sc_core::sc_out< bool > FCLK_CLK0;
sc_core::sc_out< bool > FCLK_RESET0_N;
sc_core::sc_out< sc_dt::sc_bv<54> > MIO;
sc_core::sc_out< bool > DDR_CAS_n;
sc_core::sc_out< bool > DDR_CKE;
sc_core::sc_out< bool > DDR_Clk_n;
sc_core::sc_out< bool > DDR_Clk;
sc_core::sc_out< bool > DDR_CS_n;
sc_core::sc_out< bool > DDR_DRSTB;
sc_core::sc_out< bool > DDR_ODT;
sc_core::sc_out< bool > DDR_RAS_n;
sc_core::sc_out< bool > DDR_WEB;
sc_core::sc_out< sc_dt::sc_bv<3> > DDR_BankAddr;
sc_core::sc_out< sc_dt::sc_bv<15> > DDR_Addr;
sc_core::sc_out< bool > DDR_VRN;
sc_core::sc_out< bool > DDR_VRP;
sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DM;
sc_core::sc_out< sc_dt::sc_bv<32> > DDR_DQ;
sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS_n;
sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS;
sc_core::sc_out< bool > PS_SRSTB;
sc_core::sc_out< bool > PS_CLK;
sc_core::sc_out< bool > PS_PORB;
// Dummy Signals for IP Ports
protected:
virtual void before_end_of_elaboration();
private:
};
#endif // XILINX_SIMULATOR
#ifdef XM_SYSTEMC
class DllExport zynqps : public zynqps_sc
{
public:
zynqps(const sc_core::sc_module_name& nm);
virtual ~zynqps();
// module pin-to-pin RTL interface
sc_core::sc_out< bool > FCLK_CLK0;
sc_core::sc_out< bool > FCLK_RESET0_N;
sc_core::sc_inout< sc_dt::sc_bv<54> > MIO;
sc_core::sc_inout< bool > DDR_CAS_n;
sc_core::sc_inout< bool > DDR_CKE;
sc_core::sc_inout< bool > DDR_Clk_n;
sc_core::sc_inout< bool > DDR_Clk;
sc_core::sc_inout< bool > DDR_CS_n;
sc_core::sc_inout< bool > DDR_DRSTB;
sc_core::sc_inout< bool > DDR_ODT;
sc_core::sc_inout< bool > DDR_RAS_n;
sc_core::sc_inout< bool > DDR_WEB;
sc_core::sc_inout< sc_dt::sc_bv<3> > DDR_BankAddr;
sc_core::sc_inout< sc_dt::sc_bv<15> > DDR_Addr;
sc_core::sc_inout< bool > DDR_VRN;
sc_core::sc_inout< bool > DDR_VRP;
sc_core::sc_inout< sc_dt::sc_bv<4> > DDR_DM;
sc_core::sc_inout< sc_dt::sc_bv<32> > DDR_DQ;
sc_core::sc_inout< sc_dt::sc_bv<4> > DDR_DQS_n;
sc_core::sc_inout< sc_dt::sc_bv<4> > DDR_DQS;
sc_core::sc_inout< bool > PS_SRSTB;
sc_core::sc_inout< bool > PS_CLK;
sc_core::sc_inout< bool > PS_PORB;
// Dummy Signals for IP Ports
protected:
virtual void before_end_of_elaboration();
private:
};
#endif // XM_SYSTEMC
#ifdef RIVIERA
class DllExport zynqps : public zynqps_sc
{
public:
zynqps(const sc_core::sc_module_name& nm);
virtual ~zynqps();
// module pin-to-pin RTL interface
sc_core::sc_out< bool > FCLK_CLK0;
sc_core::sc_out< bool > FCLK_RESET0_N;
sc_core::sc_out< sc_dt::sc_bv<54> > MIO;
sc_core::sc_out< bool > DDR_CAS_n;
sc_core::sc_out< bool > DDR_CKE;
sc_core::sc_out< bool > DDR_Clk_n;
sc_core::sc_out< bool > DDR_Clk;
sc_core::sc_out< bool > DDR_CS_n;
sc_core::sc_out< bool > DDR_DRSTB;
sc_core::sc_out< bool > DDR_ODT;
sc_core::sc_out< bool > DDR_RAS_n;
sc_core::sc_out< bool > DDR_WEB;
sc_core::sc_out< sc_dt::sc_bv<3> > DDR_BankAddr;
sc_core::sc_out< sc_dt::sc_bv<15> > DDR_Addr;
sc_core::sc_out< bool > DDR_VRN;
sc_core::sc_out< bool > DDR_VRP;
sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DM;
sc_core::sc_out< sc_dt::sc_bv<32> > DDR_DQ;
sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS_n;
sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS;
sc_core::sc_out< bool > PS_SRSTB;
sc_core::sc_out< bool > PS_CLK;
sc_core::sc_out< bool > PS_PORB;
// Dummy Signals for IP Ports
protected:
virtual void before_end_of_elaboration();
private:
};
#endif // RIVIERA
#ifdef VCSSYSTEMC
class DllExport zynqps : public zynqps_sc
{
public:
zynqps(const sc_core::sc_module_name& nm);
virtual ~zynqps();
// module pin-to-pin RTL interface
sc_core::sc_out< bool > FCLK_CLK0;
sc_core::sc_out< bool > FCLK_RESET0_N;
sc_core::sc_out< sc_dt::sc_bv<54> > MIO;
sc_core::sc_out< bool > DDR_CAS_n;
sc_core::sc_out< bool > DDR_CKE;
sc_core::sc_out< bool > DDR_Clk_n;
sc_core::sc_out< bool > DDR_Clk;
sc_core::sc_out< bool > DDR_CS_n;
sc_core::sc_out< bool > DDR_DRSTB;
sc_core::sc_out< bool > DDR_ODT;
sc_core::sc_out< bool > DDR_RAS_n;
sc_core::sc_out< bool > DDR_WEB;
sc_core::sc_out< sc_dt::sc_bv<3> > DDR_BankAddr;
sc_core::sc_out< sc_dt::sc_bv<15> > DDR_Addr;
sc_core::sc_out< bool > DDR_VRN;
sc_core::sc_out< bool > DDR_VRP;
sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DM;
sc_core::sc_out< sc_dt::sc_bv<32> > DDR_DQ;
sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS_n;
sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS;
sc_core::sc_out< bool > PS_SRSTB;
sc_core::sc_out< bool > PS_CLK;
sc_core::sc_out< bool > PS_PORB;
// Dummy Signals for IP Ports
protected:
virtual void before_end_of_elaboration();
private:
// Transactor stubs
// Socket stubs
};
#endif // VCSSYSTEMC
#ifdef MTI_SYSTEMC
class DllExport zynqps : public zynqps_sc
{
public:
zynqps(const sc_core::sc_module_name& nm);
virtual ~zynqps();
// module pin-to-pin RTL interface
sc_core::sc_out< bool > FCLK_CLK0;
sc_core::sc_out< bool > FCLK_RESET0_N;
sc_core::sc_out< sc_dt::sc_bv<54> > MIO;
sc_core::sc_out< bool > DDR_CAS_n;
sc_core::sc_out< bool > DDR_CKE;
sc_core::sc_out< bool > DDR_Clk_n;
sc_core::sc_out< bool > DDR_Clk;
sc_core::sc_out< bool > DDR_CS_n;
sc_core::sc_out< bool > DDR_DRSTB;
sc_core::sc_out< bool > DDR_ODT;
sc_core::sc_out< bool > DDR_RAS_n;
sc_core::sc_out< bool > DDR_WEB;
sc_core::sc_out< sc_dt::sc_bv<3> > DDR_BankAddr;
sc_core::sc_out< sc_dt::sc_bv<15> > DDR_Addr;
sc_core::sc_out< bool > DDR_VRN;
sc_core::sc_out< bool > DDR_VRP;
sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DM;
sc_core::sc_out< sc_dt::sc_bv<32> > DDR_DQ;
sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS_n;
sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS;
sc_core::sc_out< bool > PS_SRSTB;
sc_core::sc_out< bool > PS_CLK;
sc_core::sc_out< bool > PS_PORB;
// Dummy Signals for IP Ports
protected:
virtual void before_end_of_elaboration();
private:
// Transactor stubs
// Socket stubs
};
#endif // MTI_SYSTEMC
#endif // IP_ZYNQPS_H_

912
examples/.gen/sources_1/ip/zynqps/sim/zynqps.sv Normal file
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@ -0,0 +1,912 @@
`timescale 1ns/1ps
//PORTS
bit CAN0_PHY_TX;
bit CAN0_PHY_RX;
bit CAN1_PHY_TX;
bit CAN1_PHY_RX;
bit [0 : 0] ENET0_GMII_TX_EN;
bit [0 : 0] ENET0_GMII_TX_ER;
bit ENET0_MDIO_MDC;
bit ENET0_MDIO_O;
bit ENET0_MDIO_T;
bit ENET0_PTP_DELAY_REQ_RX;
bit ENET0_PTP_DELAY_REQ_TX;
bit ENET0_PTP_PDELAY_REQ_RX;
bit ENET0_PTP_PDELAY_REQ_TX;
bit ENET0_PTP_PDELAY_RESP_RX;
bit ENET0_PTP_PDELAY_RESP_TX;
bit ENET0_PTP_SYNC_FRAME_RX;
bit ENET0_PTP_SYNC_FRAME_TX;
bit ENET0_SOF_RX;
bit ENET0_SOF_TX;
bit [7 : 0] ENET0_GMII_TXD;
bit ENET0_GMII_COL;
bit ENET0_GMII_CRS;
bit ENET0_GMII_RX_CLK;
bit ENET0_GMII_RX_DV;
bit ENET0_GMII_RX_ER;
bit ENET0_GMII_TX_CLK;
bit ENET0_MDIO_I;
bit ENET0_EXT_INTIN;
bit [7 : 0] ENET0_GMII_RXD;
bit [0 : 0] ENET1_GMII_TX_EN;
bit [0 : 0] ENET1_GMII_TX_ER;
bit ENET1_MDIO_MDC;
bit ENET1_MDIO_O;
bit ENET1_MDIO_T;
bit ENET1_PTP_DELAY_REQ_RX;
bit ENET1_PTP_DELAY_REQ_TX;
bit ENET1_PTP_PDELAY_REQ_RX;
bit ENET1_PTP_PDELAY_REQ_TX;
bit ENET1_PTP_PDELAY_RESP_RX;
bit ENET1_PTP_PDELAY_RESP_TX;
bit ENET1_PTP_SYNC_FRAME_RX;
bit ENET1_PTP_SYNC_FRAME_TX;
bit ENET1_SOF_RX;
bit ENET1_SOF_TX;
bit [7 : 0] ENET1_GMII_TXD;
bit ENET1_GMII_COL;
bit ENET1_GMII_CRS;
bit ENET1_GMII_RX_CLK;
bit ENET1_GMII_RX_DV;
bit ENET1_GMII_RX_ER;
bit ENET1_GMII_TX_CLK;
bit ENET1_MDIO_I;
bit ENET1_EXT_INTIN;
bit [7 : 0] ENET1_GMII_RXD;
bit [63 : 0] GPIO_I;
bit [63 : 0] GPIO_O;
bit [63 : 0] GPIO_T;
bit I2C0_SDA_I;
bit I2C0_SDA_O;
bit I2C0_SDA_T;
bit I2C0_SCL_I;
bit I2C0_SCL_O;
bit I2C0_SCL_T;
bit I2C1_SDA_I;
bit I2C1_SDA_O;
bit I2C1_SDA_T;
bit I2C1_SCL_I;
bit I2C1_SCL_O;
bit I2C1_SCL_T;
bit PJTAG_TCK;
bit PJTAG_TMS;
bit PJTAG_TDI;
bit PJTAG_TDO;
bit SDIO0_CLK;
bit SDIO0_CLK_FB;
bit SDIO0_CMD_O;
bit SDIO0_CMD_I;
bit SDIO0_CMD_T;
bit [3 : 0] SDIO0_DATA_I;
bit [3 : 0] SDIO0_DATA_O;
bit [3 : 0] SDIO0_DATA_T;
bit SDIO0_LED;
bit SDIO0_CDN;
bit SDIO0_WP;
bit SDIO0_BUSPOW;
bit [2 : 0] SDIO0_BUSVOLT;
bit SDIO1_CLK;
bit SDIO1_CLK_FB;
bit SDIO1_CMD_O;
bit SDIO1_CMD_I;
bit SDIO1_CMD_T;
bit [3 : 0] SDIO1_DATA_I;
bit [3 : 0] SDIO1_DATA_O;
bit [3 : 0] SDIO1_DATA_T;
bit SDIO1_LED;
bit SDIO1_CDN;
bit SDIO1_WP;
bit SDIO1_BUSPOW;
bit [2 : 0] SDIO1_BUSVOLT;
bit SPI0_SCLK_I;
bit SPI0_SCLK_O;
bit SPI0_SCLK_T;
bit SPI0_MOSI_I;
bit SPI0_MOSI_O;
bit SPI0_MOSI_T;
bit SPI0_MISO_I;
bit SPI0_MISO_O;
bit SPI0_MISO_T;
bit SPI0_SS_I;
bit SPI0_SS_O;
bit SPI0_SS1_O;
bit SPI0_SS2_O;
bit SPI0_SS_T;
bit SPI1_SCLK_I;
bit SPI1_SCLK_O;
bit SPI1_SCLK_T;
bit SPI1_MOSI_I;
bit SPI1_MOSI_O;
bit SPI1_MOSI_T;
bit SPI1_MISO_I;
bit SPI1_MISO_O;
bit SPI1_MISO_T;
bit SPI1_SS_I;
bit SPI1_SS_O;
bit SPI1_SS1_O;
bit SPI1_SS2_O;
bit SPI1_SS_T;
bit UART0_DTRN;
bit UART0_RTSN;
bit UART0_TX;
bit UART0_CTSN;
bit UART0_DCDN;
bit UART0_DSRN;
bit UART0_RIN;
bit UART0_RX;
bit UART1_DTRN;
bit UART1_RTSN;
bit UART1_TX;
bit UART1_CTSN;
bit UART1_DCDN;
bit UART1_DSRN;
bit UART1_RIN;
bit UART1_RX;
bit TTC0_WAVE0_OUT;
bit TTC0_WAVE1_OUT;
bit TTC0_WAVE2_OUT;
bit TTC0_CLK0_IN;
bit TTC0_CLK1_IN;
bit TTC0_CLK2_IN;
bit TTC1_WAVE0_OUT;
bit TTC1_WAVE1_OUT;
bit TTC1_WAVE2_OUT;
bit TTC1_CLK0_IN;
bit TTC1_CLK1_IN;
bit TTC1_CLK2_IN;
bit WDT_CLK_IN;
bit WDT_RST_OUT;
bit TRACE_CLK;
bit TRACE_CLK_OUT;
bit TRACE_CTL;
bit [1 : 0] TRACE_DATA;
bit [1 : 0] USB0_PORT_INDCTL;
bit USB0_VBUS_PWRSELECT;
bit USB0_VBUS_PWRFAULT;
bit [1 : 0] USB1_PORT_INDCTL;
bit USB1_VBUS_PWRSELECT;
bit USB1_VBUS_PWRFAULT;
bit SRAM_INTIN;
bit M_AXI_GP0_ARVALID;
bit M_AXI_GP0_AWVALID;
bit M_AXI_GP0_BREADY;
bit M_AXI_GP0_RREADY;
bit M_AXI_GP0_WLAST;
bit M_AXI_GP0_WVALID;
bit [11 : 0] M_AXI_GP0_ARID;
bit [11 : 0] M_AXI_GP0_AWID;
bit [11 : 0] M_AXI_GP0_WID;
bit [1 : 0] M_AXI_GP0_ARBURST;
bit [1 : 0] M_AXI_GP0_ARLOCK;
bit [2 : 0] M_AXI_GP0_ARSIZE;
bit [1 : 0] M_AXI_GP0_AWBURST;
bit [1 : 0] M_AXI_GP0_AWLOCK;
bit [2 : 0] M_AXI_GP0_AWSIZE;
bit [2 : 0] M_AXI_GP0_ARPROT;
bit [2 : 0] M_AXI_GP0_AWPROT;
bit [31 : 0] M_AXI_GP0_ARADDR;
bit [31 : 0] M_AXI_GP0_AWADDR;
bit [31 : 0] M_AXI_GP0_WDATA;
bit [3 : 0] M_AXI_GP0_ARCACHE;
bit [3 : 0] M_AXI_GP0_ARLEN;
bit [3 : 0] M_AXI_GP0_ARQOS;
bit [3 : 0] M_AXI_GP0_AWCACHE;
bit [3 : 0] M_AXI_GP0_AWLEN;
bit [3 : 0] M_AXI_GP0_AWQOS;
bit [3 : 0] M_AXI_GP0_WSTRB;
bit M_AXI_GP0_ACLK;
bit M_AXI_GP0_ARREADY;
bit M_AXI_GP0_AWREADY;
bit M_AXI_GP0_BVALID;
bit M_AXI_GP0_RLAST;
bit M_AXI_GP0_RVALID;
bit M_AXI_GP0_WREADY;
bit [11 : 0] M_AXI_GP0_BID;
bit [11 : 0] M_AXI_GP0_RID;
bit [1 : 0] M_AXI_GP0_BRESP;
bit [1 : 0] M_AXI_GP0_RRESP;
bit [31 : 0] M_AXI_GP0_RDATA;
bit M_AXI_GP1_ARVALID;
bit M_AXI_GP1_AWVALID;
bit M_AXI_GP1_BREADY;
bit M_AXI_GP1_RREADY;
bit M_AXI_GP1_WLAST;
bit M_AXI_GP1_WVALID;
bit [11 : 0] M_AXI_GP1_ARID;
bit [11 : 0] M_AXI_GP1_AWID;
bit [11 : 0] M_AXI_GP1_WID;
bit [1 : 0] M_AXI_GP1_ARBURST;
bit [1 : 0] M_AXI_GP1_ARLOCK;
bit [2 : 0] M_AXI_GP1_ARSIZE;
bit [1 : 0] M_AXI_GP1_AWBURST;
bit [1 : 0] M_AXI_GP1_AWLOCK;
bit [2 : 0] M_AXI_GP1_AWSIZE;
bit [2 : 0] M_AXI_GP1_ARPROT;
bit [2 : 0] M_AXI_GP1_AWPROT;
bit [31 : 0] M_AXI_GP1_ARADDR;
bit [31 : 0] M_AXI_GP1_AWADDR;
bit [31 : 0] M_AXI_GP1_WDATA;
bit [3 : 0] M_AXI_GP1_ARCACHE;
bit [3 : 0] M_AXI_GP1_ARLEN;
bit [3 : 0] M_AXI_GP1_ARQOS;
bit [3 : 0] M_AXI_GP1_AWCACHE;
bit [3 : 0] M_AXI_GP1_AWLEN;
bit [3 : 0] M_AXI_GP1_AWQOS;
bit [3 : 0] M_AXI_GP1_WSTRB;
bit M_AXI_GP1_ACLK;
bit M_AXI_GP1_ARREADY;
bit M_AXI_GP1_AWREADY;
bit M_AXI_GP1_BVALID;
bit M_AXI_GP1_RLAST;
bit M_AXI_GP1_RVALID;
bit M_AXI_GP1_WREADY;
bit [11 : 0] M_AXI_GP1_BID;
bit [11 : 0] M_AXI_GP1_RID;
bit [1 : 0] M_AXI_GP1_BRESP;
bit [1 : 0] M_AXI_GP1_RRESP;
bit [31 : 0] M_AXI_GP1_RDATA;
bit S_AXI_GP0_ARREADY;
bit S_AXI_GP0_AWREADY;
bit S_AXI_GP0_BVALID;
bit S_AXI_GP0_RLAST;
bit S_AXI_GP0_RVALID;
bit S_AXI_GP0_WREADY;
bit [1 : 0] S_AXI_GP0_BRESP;
bit [1 : 0] S_AXI_GP0_RRESP;
bit [31 : 0] S_AXI_GP0_RDATA;
bit [5 : 0] S_AXI_GP0_BID;
bit [5 : 0] S_AXI_GP0_RID;
bit S_AXI_GP0_ACLK;
bit S_AXI_GP0_ARVALID;
bit S_AXI_GP0_AWVALID;
bit S_AXI_GP0_BREADY;
bit S_AXI_GP0_RREADY;
bit S_AXI_GP0_WLAST;
bit S_AXI_GP0_WVALID;
bit [1 : 0] S_AXI_GP0_ARBURST;
bit [1 : 0] S_AXI_GP0_ARLOCK;
bit [2 : 0] S_AXI_GP0_ARSIZE;
bit [1 : 0] S_AXI_GP0_AWBURST;
bit [1 : 0] S_AXI_GP0_AWLOCK;
bit [2 : 0] S_AXI_GP0_AWSIZE;
bit [2 : 0] S_AXI_GP0_ARPROT;
bit [2 : 0] S_AXI_GP0_AWPROT;
bit [31 : 0] S_AXI_GP0_ARADDR;
bit [31 : 0] S_AXI_GP0_AWADDR;
bit [31 : 0] S_AXI_GP0_WDATA;
bit [3 : 0] S_AXI_GP0_ARCACHE;
bit [3 : 0] S_AXI_GP0_ARLEN;
bit [3 : 0] S_AXI_GP0_ARQOS;
bit [3 : 0] S_AXI_GP0_AWCACHE;
bit [3 : 0] S_AXI_GP0_AWLEN;
bit [3 : 0] S_AXI_GP0_AWQOS;
bit [3 : 0] S_AXI_GP0_WSTRB;
bit [5 : 0] S_AXI_GP0_ARID;
bit [5 : 0] S_AXI_GP0_AWID;
bit [5 : 0] S_AXI_GP0_WID;
bit S_AXI_GP1_ARREADY;
bit S_AXI_GP1_AWREADY;
bit S_AXI_GP1_BVALID;
bit S_AXI_GP1_RLAST;
bit S_AXI_GP1_RVALID;
bit S_AXI_GP1_WREADY;
bit [1 : 0] S_AXI_GP1_BRESP;
bit [1 : 0] S_AXI_GP1_RRESP;
bit [31 : 0] S_AXI_GP1_RDATA;
bit [5 : 0] S_AXI_GP1_BID;
bit [5 : 0] S_AXI_GP1_RID;
bit S_AXI_GP1_ACLK;
bit S_AXI_GP1_ARVALID;
bit S_AXI_GP1_AWVALID;
bit S_AXI_GP1_BREADY;
bit S_AXI_GP1_RREADY;
bit S_AXI_GP1_WLAST;
bit S_AXI_GP1_WVALID;
bit [1 : 0] S_AXI_GP1_ARBURST;
bit [1 : 0] S_AXI_GP1_ARLOCK;
bit [2 : 0] S_AXI_GP1_ARSIZE;
bit [1 : 0] S_AXI_GP1_AWBURST;
bit [1 : 0] S_AXI_GP1_AWLOCK;
bit [2 : 0] S_AXI_GP1_AWSIZE;
bit [2 : 0] S_AXI_GP1_ARPROT;
bit [2 : 0] S_AXI_GP1_AWPROT;
bit [31 : 0] S_AXI_GP1_ARADDR;
bit [31 : 0] S_AXI_GP1_AWADDR;
bit [31 : 0] S_AXI_GP1_WDATA;
bit [3 : 0] S_AXI_GP1_ARCACHE;
bit [3 : 0] S_AXI_GP1_ARLEN;
bit [3 : 0] S_AXI_GP1_ARQOS;
bit [3 : 0] S_AXI_GP1_AWCACHE;
bit [3 : 0] S_AXI_GP1_AWLEN;
bit [3 : 0] S_AXI_GP1_AWQOS;
bit [3 : 0] S_AXI_GP1_WSTRB;
bit [5 : 0] S_AXI_GP1_ARID;
bit [5 : 0] S_AXI_GP1_AWID;
bit [5 : 0] S_AXI_GP1_WID;
bit S_AXI_ACP_ARREADY;
bit S_AXI_ACP_AWREADY;
bit S_AXI_ACP_BVALID;
bit S_AXI_ACP_RLAST;
bit S_AXI_ACP_RVALID;
bit S_AXI_ACP_WREADY;
bit [1 : 0] S_AXI_ACP_BRESP;
bit [1 : 0] S_AXI_ACP_RRESP;
bit [2 : 0] S_AXI_ACP_BID;
bit [2 : 0] S_AXI_ACP_RID;
bit [63 : 0] S_AXI_ACP_RDATA;
bit S_AXI_ACP_ACLK;
bit S_AXI_ACP_ARVALID;
bit S_AXI_ACP_AWVALID;
bit S_AXI_ACP_BREADY;
bit S_AXI_ACP_RREADY;
bit S_AXI_ACP_WLAST;
bit S_AXI_ACP_WVALID;
bit [2 : 0] S_AXI_ACP_ARID;
bit [2 : 0] S_AXI_ACP_ARPROT;
bit [2 : 0] S_AXI_ACP_AWID;
bit [2 : 0] S_AXI_ACP_AWPROT;
bit [2 : 0] S_AXI_ACP_WID;
bit [31 : 0] S_AXI_ACP_ARADDR;
bit [31 : 0] S_AXI_ACP_AWADDR;
bit [3 : 0] S_AXI_ACP_ARCACHE;
bit [3 : 0] S_AXI_ACP_ARLEN;
bit [3 : 0] S_AXI_ACP_ARQOS;
bit [3 : 0] S_AXI_ACP_AWCACHE;
bit [3 : 0] S_AXI_ACP_AWLEN;
bit [3 : 0] S_AXI_ACP_AWQOS;
bit [1 : 0] S_AXI_ACP_ARBURST;
bit [1 : 0] S_AXI_ACP_ARLOCK;
bit [2 : 0] S_AXI_ACP_ARSIZE;
bit [1 : 0] S_AXI_ACP_AWBURST;
bit [1 : 0] S_AXI_ACP_AWLOCK;
bit [2 : 0] S_AXI_ACP_AWSIZE;
bit [4 : 0] S_AXI_ACP_ARUSER;
bit [4 : 0] S_AXI_ACP_AWUSER;
bit [63 : 0] S_AXI_ACP_WDATA;
bit [7 : 0] S_AXI_ACP_WSTRB;
bit S_AXI_HP0_ARREADY;
bit S_AXI_HP0_AWREADY;
bit S_AXI_HP0_BVALID;
bit S_AXI_HP0_RLAST;
bit S_AXI_HP0_RVALID;
bit S_AXI_HP0_WREADY;
bit [1 : 0] S_AXI_HP0_BRESP;
bit [1 : 0] S_AXI_HP0_RRESP;
bit [5 : 0] S_AXI_HP0_BID;
bit [5 : 0] S_AXI_HP0_RID;
bit [63 : 0] S_AXI_HP0_RDATA;
bit [7 : 0] S_AXI_HP0_RCOUNT;
bit [7 : 0] S_AXI_HP0_WCOUNT;
bit [2 : 0] S_AXI_HP0_RACOUNT;
bit [5 : 0] S_AXI_HP0_WACOUNT;
bit S_AXI_HP0_ACLK;
bit S_AXI_HP0_ARVALID;
bit S_AXI_HP0_AWVALID;
bit S_AXI_HP0_BREADY;
bit S_AXI_HP0_RDISSUECAP1_EN;
bit S_AXI_HP0_RREADY;
bit S_AXI_HP0_WLAST;
bit S_AXI_HP0_WRISSUECAP1_EN;
bit S_AXI_HP0_WVALID;
bit [1 : 0] S_AXI_HP0_ARBURST;
bit [1 : 0] S_AXI_HP0_ARLOCK;
bit [2 : 0] S_AXI_HP0_ARSIZE;
bit [1 : 0] S_AXI_HP0_AWBURST;
bit [1 : 0] S_AXI_HP0_AWLOCK;
bit [2 : 0] S_AXI_HP0_AWSIZE;
bit [2 : 0] S_AXI_HP0_ARPROT;
bit [2 : 0] S_AXI_HP0_AWPROT;
bit [31 : 0] S_AXI_HP0_ARADDR;
bit [31 : 0] S_AXI_HP0_AWADDR;
bit [3 : 0] S_AXI_HP0_ARCACHE;
bit [3 : 0] S_AXI_HP0_ARLEN;
bit [3 : 0] S_AXI_HP0_ARQOS;
bit [3 : 0] S_AXI_HP0_AWCACHE;
bit [3 : 0] S_AXI_HP0_AWLEN;
bit [3 : 0] S_AXI_HP0_AWQOS;
bit [5 : 0] S_AXI_HP0_ARID;
bit [5 : 0] S_AXI_HP0_AWID;
bit [5 : 0] S_AXI_HP0_WID;
bit [63 : 0] S_AXI_HP0_WDATA;
bit [7 : 0] S_AXI_HP0_WSTRB;
bit S_AXI_HP1_ARREADY;
bit S_AXI_HP1_AWREADY;
bit S_AXI_HP1_BVALID;
bit S_AXI_HP1_RLAST;
bit S_AXI_HP1_RVALID;
bit S_AXI_HP1_WREADY;
bit [1 : 0] S_AXI_HP1_BRESP;
bit [1 : 0] S_AXI_HP1_RRESP;
bit [5 : 0] S_AXI_HP1_BID;
bit [5 : 0] S_AXI_HP1_RID;
bit [63 : 0] S_AXI_HP1_RDATA;
bit [7 : 0] S_AXI_HP1_RCOUNT;
bit [7 : 0] S_AXI_HP1_WCOUNT;
bit [2 : 0] S_AXI_HP1_RACOUNT;
bit [5 : 0] S_AXI_HP1_WACOUNT;
bit S_AXI_HP1_ACLK;
bit S_AXI_HP1_ARVALID;
bit S_AXI_HP1_AWVALID;
bit S_AXI_HP1_BREADY;
bit S_AXI_HP1_RDISSUECAP1_EN;
bit S_AXI_HP1_RREADY;
bit S_AXI_HP1_WLAST;
bit S_AXI_HP1_WRISSUECAP1_EN;
bit S_AXI_HP1_WVALID;
bit [1 : 0] S_AXI_HP1_ARBURST;
bit [1 : 0] S_AXI_HP1_ARLOCK;
bit [2 : 0] S_AXI_HP1_ARSIZE;
bit [1 : 0] S_AXI_HP1_AWBURST;
bit [1 : 0] S_AXI_HP1_AWLOCK;
bit [2 : 0] S_AXI_HP1_AWSIZE;
bit [2 : 0] S_AXI_HP1_ARPROT;
bit [2 : 0] S_AXI_HP1_AWPROT;
bit [31 : 0] S_AXI_HP1_ARADDR;
bit [31 : 0] S_AXI_HP1_AWADDR;
bit [3 : 0] S_AXI_HP1_ARCACHE;
bit [3 : 0] S_AXI_HP1_ARLEN;
bit [3 : 0] S_AXI_HP1_ARQOS;
bit [3 : 0] S_AXI_HP1_AWCACHE;
bit [3 : 0] S_AXI_HP1_AWLEN;
bit [3 : 0] S_AXI_HP1_AWQOS;
bit [5 : 0] S_AXI_HP1_ARID;
bit [5 : 0] S_AXI_HP1_AWID;
bit [5 : 0] S_AXI_HP1_WID;
bit [63 : 0] S_AXI_HP1_WDATA;
bit [7 : 0] S_AXI_HP1_WSTRB;
bit S_AXI_HP2_ARREADY;
bit S_AXI_HP2_AWREADY;
bit S_AXI_HP2_BVALID;
bit S_AXI_HP2_RLAST;
bit S_AXI_HP2_RVALID;
bit S_AXI_HP2_WREADY;
bit [1 : 0] S_AXI_HP2_BRESP;
bit [1 : 0] S_AXI_HP2_RRESP;
bit [5 : 0] S_AXI_HP2_BID;
bit [5 : 0] S_AXI_HP2_RID;
bit [63 : 0] S_AXI_HP2_RDATA;
bit [7 : 0] S_AXI_HP2_RCOUNT;
bit [7 : 0] S_AXI_HP2_WCOUNT;
bit [2 : 0] S_AXI_HP2_RACOUNT;
bit [5 : 0] S_AXI_HP2_WACOUNT;
bit S_AXI_HP2_ACLK;
bit S_AXI_HP2_ARVALID;
bit S_AXI_HP2_AWVALID;
bit S_AXI_HP2_BREADY;
bit S_AXI_HP2_RDISSUECAP1_EN;
bit S_AXI_HP2_RREADY;
bit S_AXI_HP2_WLAST;
bit S_AXI_HP2_WRISSUECAP1_EN;
bit S_AXI_HP2_WVALID;
bit [1 : 0] S_AXI_HP2_ARBURST;
bit [1 : 0] S_AXI_HP2_ARLOCK;
bit [2 : 0] S_AXI_HP2_ARSIZE;
bit [1 : 0] S_AXI_HP2_AWBURST;
bit [1 : 0] S_AXI_HP2_AWLOCK;
bit [2 : 0] S_AXI_HP2_AWSIZE;
bit [2 : 0] S_AXI_HP2_ARPROT;
bit [2 : 0] S_AXI_HP2_AWPROT;
bit [31 : 0] S_AXI_HP2_ARADDR;
bit [31 : 0] S_AXI_HP2_AWADDR;
bit [3 : 0] S_AXI_HP2_ARCACHE;
bit [3 : 0] S_AXI_HP2_ARLEN;
bit [3 : 0] S_AXI_HP2_ARQOS;
bit [3 : 0] S_AXI_HP2_AWCACHE;
bit [3 : 0] S_AXI_HP2_AWLEN;
bit [3 : 0] S_AXI_HP2_AWQOS;
bit [5 : 0] S_AXI_HP2_ARID;
bit [5 : 0] S_AXI_HP2_AWID;
bit [5 : 0] S_AXI_HP2_WID;
bit [63 : 0] S_AXI_HP2_WDATA;
bit [7 : 0] S_AXI_HP2_WSTRB;
bit S_AXI_HP3_ARREADY;
bit S_AXI_HP3_AWREADY;
bit S_AXI_HP3_BVALID;
bit S_AXI_HP3_RLAST;
bit S_AXI_HP3_RVALID;
bit S_AXI_HP3_WREADY;
bit [1 : 0] S_AXI_HP3_BRESP;
bit [1 : 0] S_AXI_HP3_RRESP;
bit [5 : 0] S_AXI_HP3_BID;
bit [5 : 0] S_AXI_HP3_RID;
bit [63 : 0] S_AXI_HP3_RDATA;
bit [7 : 0] S_AXI_HP3_RCOUNT;
bit [7 : 0] S_AXI_HP3_WCOUNT;
bit [2 : 0] S_AXI_HP3_RACOUNT;
bit [5 : 0] S_AXI_HP3_WACOUNT;
bit S_AXI_HP3_ACLK;
bit S_AXI_HP3_ARVALID;
bit S_AXI_HP3_AWVALID;
bit S_AXI_HP3_BREADY;
bit S_AXI_HP3_RDISSUECAP1_EN;
bit S_AXI_HP3_RREADY;
bit S_AXI_HP3_WLAST;
bit S_AXI_HP3_WRISSUECAP1_EN;
bit S_AXI_HP3_WVALID;
bit [1 : 0] S_AXI_HP3_ARBURST;
bit [1 : 0] S_AXI_HP3_ARLOCK;
bit [2 : 0] S_AXI_HP3_ARSIZE;
bit [1 : 0] S_AXI_HP3_AWBURST;
bit [1 : 0] S_AXI_HP3_AWLOCK;
bit [2 : 0] S_AXI_HP3_AWSIZE;
bit [2 : 0] S_AXI_HP3_ARPROT;
bit [2 : 0] S_AXI_HP3_AWPROT;
bit [31 : 0] S_AXI_HP3_ARADDR;
bit [31 : 0] S_AXI_HP3_AWADDR;
bit [3 : 0] S_AXI_HP3_ARCACHE;
bit [3 : 0] S_AXI_HP3_ARLEN;
bit [3 : 0] S_AXI_HP3_ARQOS;
bit [3 : 0] S_AXI_HP3_AWCACHE;
bit [3 : 0] S_AXI_HP3_AWLEN;
bit [3 : 0] S_AXI_HP3_AWQOS;
bit [5 : 0] S_AXI_HP3_ARID;
bit [5 : 0] S_AXI_HP3_AWID;
bit [5 : 0] S_AXI_HP3_WID;
bit [63 : 0] S_AXI_HP3_WDATA;
bit [7 : 0] S_AXI_HP3_WSTRB;
bit IRQ_P2F_DMAC_ABORT;
bit IRQ_P2F_DMAC0;
bit IRQ_P2F_DMAC1;
bit IRQ_P2F_DMAC2;
bit IRQ_P2F_DMAC3;
bit IRQ_P2F_DMAC4;
bit IRQ_P2F_DMAC5;
bit IRQ_P2F_DMAC6;
bit IRQ_P2F_DMAC7;
bit IRQ_P2F_SMC;
bit IRQ_P2F_QSPI;
bit IRQ_P2F_CTI;
bit IRQ_P2F_GPIO;
bit IRQ_P2F_USB0;
bit IRQ_P2F_ENET0;
bit IRQ_P2F_ENET_WAKE0;
bit IRQ_P2F_SDIO0;
bit IRQ_P2F_I2C0;
bit IRQ_P2F_SPI0;
bit IRQ_P2F_UART0;
bit IRQ_P2F_CAN0;
bit IRQ_P2F_USB1;
bit IRQ_P2F_ENET1;
bit IRQ_P2F_ENET_WAKE1;
bit IRQ_P2F_SDIO1;
bit IRQ_P2F_I2C1;
bit IRQ_P2F_SPI1;
bit IRQ_P2F_UART1;
bit IRQ_P2F_CAN1;
bit [0 : 0] IRQ_F2P;
bit Core0_nFIQ;
bit Core0_nIRQ;
bit Core1_nFIQ;
bit Core1_nIRQ;
bit [1 : 0] DMA0_DATYPE;
bit DMA0_DAVALID;
bit DMA0_DRREADY;
bit [1 : 0] DMA1_DATYPE;
bit DMA1_DAVALID;
bit DMA1_DRREADY;
bit [1 : 0] DMA2_DATYPE;
bit DMA2_DAVALID;
bit DMA2_DRREADY;
bit [1 : 0] DMA3_DATYPE;
bit DMA3_DAVALID;
bit DMA3_DRREADY;
bit DMA0_ACLK;
bit DMA0_DAREADY;
bit DMA0_DRLAST;
bit DMA0_DRVALID;
bit DMA1_ACLK;
bit DMA1_DAREADY;
bit DMA1_DRLAST;
bit DMA1_DRVALID;
bit DMA2_ACLK;
bit DMA2_DAREADY;
bit DMA2_DRLAST;
bit DMA2_DRVALID;
bit DMA3_ACLK;
bit DMA3_DAREADY;
bit DMA3_DRLAST;
bit DMA3_DRVALID;
bit [1 : 0] DMA0_DRTYPE;
bit [1 : 0] DMA1_DRTYPE;
bit [1 : 0] DMA2_DRTYPE;
bit [1 : 0] DMA3_DRTYPE;
bit FCLK_CLK0;
bit FCLK_CLK1;
bit FCLK_CLK2;
bit FCLK_CLK3;
bit FCLK_CLKTRIG0_N;
bit FCLK_CLKTRIG1_N;
bit FCLK_CLKTRIG2_N;
bit FCLK_CLKTRIG3_N;
bit FCLK_RESET0_N;
bit FCLK_RESET1_N;
bit FCLK_RESET2_N;
bit FCLK_RESET3_N;
bit [31 : 0] FTMD_TRACEIN_DATA;
bit FTMD_TRACEIN_VALID;
bit FTMD_TRACEIN_CLK;
bit [3 : 0] FTMD_TRACEIN_ATID;
bit FTMT_F2P_TRIG_0;
bit FTMT_F2P_TRIGACK_0;
bit FTMT_F2P_TRIG_1;
bit FTMT_F2P_TRIGACK_1;
bit FTMT_F2P_TRIG_2;
bit FTMT_F2P_TRIGACK_2;
bit FTMT_F2P_TRIG_3;
bit FTMT_F2P_TRIGACK_3;
bit [31 : 0] FTMT_F2P_DEBUG;
bit FTMT_P2F_TRIGACK_0;
bit FTMT_P2F_TRIG_0;
bit FTMT_P2F_TRIGACK_1;
bit FTMT_P2F_TRIG_1;
bit FTMT_P2F_TRIGACK_2;
bit FTMT_P2F_TRIG_2;
bit FTMT_P2F_TRIGACK_3;
bit FTMT_P2F_TRIG_3;
bit [31 : 0] FTMT_P2F_DEBUG;
bit FPGA_IDLE_N;
bit EVENT_EVENTO;
bit [1 : 0] EVENT_STANDBYWFE;
bit [1 : 0] EVENT_STANDBYWFI;
bit EVENT_EVENTI;
bit [3 : 0] DDR_ARB;
bit [53 : 0] MIO;
bit DDR_CAS_n;
bit DDR_CKE;
bit DDR_Clk_n;
bit DDR_Clk;
bit DDR_CS_n;
bit DDR_DRSTB;
bit DDR_ODT;
bit DDR_RAS_n;
bit DDR_WEB;
bit [2 : 0] DDR_BankAddr;
bit [14 : 0] DDR_Addr;
bit DDR_VRN;
bit DDR_VRP;
bit [3 : 0] DDR_DM;
bit [31 : 0] DDR_DQ;
bit [3 : 0] DDR_DQS_n;
bit [3 : 0] DDR_DQS;
bit PS_SRSTB;
bit PS_CLK;
bit PS_PORB;
//MODULE DECLARATION
module zynqps (
FCLK_CLK0,
FCLK_RESET0_N,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB
);
//PARAMETERS
parameter C_EN_EMIO_PJTAG = 0;
parameter C_EN_EMIO_ENET0 = 0;
parameter C_EN_EMIO_ENET1 = 0;
parameter C_EN_EMIO_TRACE = 0;
parameter C_INCLUDE_TRACE_BUFFER = 0;
parameter C_TRACE_BUFFER_FIFO_SIZE = 128;
parameter USE_TRACE_DATA_EDGE_DETECTOR = 0;
parameter C_TRACE_PIPELINE_WIDTH = 8;
parameter C_TRACE_BUFFER_CLOCK_DELAY = 12;
parameter C_EMIO_GPIO_WIDTH = 64;
parameter C_INCLUDE_ACP_TRANS_CHECK = 0;
parameter C_USE_DEFAULT_ACP_USER_VAL = 0;
parameter C_S_AXI_ACP_ARUSER_VAL = 31;
parameter C_S_AXI_ACP_AWUSER_VAL = 31;
parameter C_M_AXI_GP0_ID_WIDTH = 12;
parameter C_M_AXI_GP0_ENABLE_STATIC_REMAP = 0;
parameter C_M_AXI_GP1_ID_WIDTH = 12;
parameter C_M_AXI_GP1_ENABLE_STATIC_REMAP = 0;
parameter C_S_AXI_GP0_ID_WIDTH = 6;
parameter C_S_AXI_GP1_ID_WIDTH = 6;
parameter C_S_AXI_ACP_ID_WIDTH = 3;
parameter C_S_AXI_HP0_ID_WIDTH = 6;
parameter C_S_AXI_HP0_DATA_WIDTH = 64;
parameter C_S_AXI_HP1_ID_WIDTH = 6;
parameter C_S_AXI_HP1_DATA_WIDTH = 64;
parameter C_S_AXI_HP2_ID_WIDTH = 6;
parameter C_S_AXI_HP2_DATA_WIDTH = 64;
parameter C_S_AXI_HP3_ID_WIDTH = 6;
parameter C_S_AXI_HP3_DATA_WIDTH = 64;
parameter C_M_AXI_GP0_THREAD_ID_WIDTH = 12;
parameter C_M_AXI_GP1_THREAD_ID_WIDTH = 12;
parameter C_NUM_F2P_INTR_INPUTS = 1;
parameter C_IRQ_F2P_MODE = "DIRECT";
parameter C_DQ_WIDTH = 32;
parameter C_DQS_WIDTH = 4;
parameter C_DM_WIDTH = 4;
parameter C_MIO_PRIMITIVE = 54;
parameter C_TRACE_INTERNAL_WIDTH = 2;
parameter C_USE_AXI_NONSECURE = 0;
parameter C_USE_M_AXI_GP0 = 0;
parameter C_USE_M_AXI_GP1 = 0;
parameter C_USE_S_AXI_GP0 = 0;
parameter C_USE_S_AXI_GP1 = 0;
parameter C_USE_S_AXI_HP0 = 0;
parameter C_USE_S_AXI_HP1 = 0;
parameter C_USE_S_AXI_HP2 = 0;
parameter C_USE_S_AXI_HP3 = 0;
parameter C_USE_S_AXI_ACP = 0;
parameter C_PS7_SI_REV = "PRODUCTION";
parameter C_FCLK_CLK0_BUF = "TRUE";
parameter C_FCLK_CLK1_BUF = "FALSE";
parameter C_FCLK_CLK2_BUF = "FALSE";
parameter C_FCLK_CLK3_BUF = "FALSE";
parameter C_PACKAGE_NAME = "clg400";
parameter C_GP0_EN_MODIFIABLE_TXN = "1";
parameter C_GP1_EN_MODIFIABLE_TXN = "1";
//INPUT AND OUTPUT PORTS
output FCLK_CLK0;
output FCLK_RESET0_N;
inout [53 : 0] MIO;
inout DDR_CAS_n;
inout DDR_CKE;
inout DDR_Clk_n;
inout DDR_Clk;
inout DDR_CS_n;
inout DDR_DRSTB;
inout DDR_ODT;
inout DDR_RAS_n;
inout DDR_WEB;
inout [2 : 0] DDR_BankAddr;
inout [14 : 0] DDR_Addr;
inout DDR_VRN;
inout DDR_VRP;
inout [3 : 0] DDR_DM;
inout [31 : 0] DDR_DQ;
inout [3 : 0] DDR_DQS_n;
inout [3 : 0] DDR_DQS;
inout PS_SRSTB;
inout PS_CLK;
inout PS_PORB;
//REG DECLARATIONS
reg FCLK_CLK0;
reg FCLK_RESET0_N;
string ip_name;
reg disable_port;
//DPI DECLARATIONS
import "DPI-C" function void ps7_set_ip_context(input string ip_name);
import "DPI-C" function void ps7_set_str_param(input string name,input string val);
import "DPI-C" function void ps7_set_int_param(input string name,input longint val);
import "DPI-C" function void ps7_init_c_model();
import "DPI-C" function void ps7_simulate_single_cycle_FCLK_CLK0();
export "DPI-C" function ps7_stop_sim;
function void ps7_stop_sim();
$display("End of simulation");
$finish(0);
endfunction
export "DPI-C" function ps7_get_time;
function real ps7_get_time();
ps7_get_time = $time;
endfunction
export "DPI-C" function ps7_set_output_pins_FCLK_RESET0_N;
function void ps7_set_output_pins_FCLK_RESET0_N(int value);
FCLK_RESET0_N = value;
endfunction
export "DPI-C" function ps7_set_output_pins_FCLK_RESET1_N;
function void ps7_set_output_pins_FCLK_RESET1_N(int value);
FCLK_RESET1_N = value;
endfunction
export "DPI-C" function ps7_set_output_pins_FCLK_RESET2_N;
function void ps7_set_output_pins_FCLK_RESET2_N(int value);
FCLK_RESET2_N = value;
endfunction
export "DPI-C" function ps7_set_output_pins_FCLK_RESET3_N;
function void ps7_set_output_pins_FCLK_RESET3_N(int value);
FCLK_RESET3_N = value;
endfunction
//INITIAL BLOCK
initial
begin
$sformat(ip_name,"%m");
ps7_set_ip_context(ip_name);
ps7_set_int_param ( "C_EN_EMIO_PJTAG",C_EN_EMIO_PJTAG );
ps7_set_int_param ( "C_EN_EMIO_ENET0",C_EN_EMIO_ENET0 );
ps7_set_int_param ( "C_EN_EMIO_ENET1",C_EN_EMIO_ENET1 );
ps7_set_int_param ( "C_EN_EMIO_TRACE",C_EN_EMIO_TRACE );
ps7_set_int_param ( "C_INCLUDE_TRACE_BUFFER",C_INCLUDE_TRACE_BUFFER );
ps7_set_int_param ( "C_TRACE_BUFFER_FIFO_SIZE",C_TRACE_BUFFER_FIFO_SIZE );
ps7_set_int_param ( "USE_TRACE_DATA_EDGE_DETECTOR",USE_TRACE_DATA_EDGE_DETECTOR );
ps7_set_int_param ( "C_TRACE_PIPELINE_WIDTH",C_TRACE_PIPELINE_WIDTH );
ps7_set_int_param ( "C_TRACE_BUFFER_CLOCK_DELAY",C_TRACE_BUFFER_CLOCK_DELAY );
ps7_set_int_param ( "C_EMIO_GPIO_WIDTH",C_EMIO_GPIO_WIDTH );
ps7_set_int_param ( "C_INCLUDE_ACP_TRANS_CHECK",C_INCLUDE_ACP_TRANS_CHECK );
ps7_set_int_param ( "C_USE_DEFAULT_ACP_USER_VAL",C_USE_DEFAULT_ACP_USER_VAL );
ps7_set_int_param ( "C_S_AXI_ACP_ARUSER_VAL",C_S_AXI_ACP_ARUSER_VAL );
ps7_set_int_param ( "C_S_AXI_ACP_AWUSER_VAL",C_S_AXI_ACP_AWUSER_VAL );
ps7_set_int_param ( "C_M_AXI_GP0_ID_WIDTH",C_M_AXI_GP0_ID_WIDTH );
ps7_set_int_param ( "C_M_AXI_GP0_ENABLE_STATIC_REMAP",C_M_AXI_GP0_ENABLE_STATIC_REMAP );
ps7_set_int_param ( "C_M_AXI_GP1_ID_WIDTH",C_M_AXI_GP1_ID_WIDTH );
ps7_set_int_param ( "C_M_AXI_GP1_ENABLE_STATIC_REMAP",C_M_AXI_GP1_ENABLE_STATIC_REMAP );
ps7_set_int_param ( "C_S_AXI_GP0_ID_WIDTH",C_S_AXI_GP0_ID_WIDTH );
ps7_set_int_param ( "C_S_AXI_GP1_ID_WIDTH",C_S_AXI_GP1_ID_WIDTH );
ps7_set_int_param ( "C_S_AXI_ACP_ID_WIDTH",C_S_AXI_ACP_ID_WIDTH );
ps7_set_int_param ( "C_S_AXI_HP0_ID_WIDTH",C_S_AXI_HP0_ID_WIDTH );
ps7_set_int_param ( "C_S_AXI_HP0_DATA_WIDTH",C_S_AXI_HP0_DATA_WIDTH );
ps7_set_int_param ( "C_S_AXI_HP1_ID_WIDTH",C_S_AXI_HP1_ID_WIDTH );
ps7_set_int_param ( "C_S_AXI_HP1_DATA_WIDTH",C_S_AXI_HP1_DATA_WIDTH );
ps7_set_int_param ( "C_S_AXI_HP2_ID_WIDTH",C_S_AXI_HP2_ID_WIDTH );
ps7_set_int_param ( "C_S_AXI_HP2_DATA_WIDTH",C_S_AXI_HP2_DATA_WIDTH );
ps7_set_int_param ( "C_S_AXI_HP3_ID_WIDTH",C_S_AXI_HP3_ID_WIDTH );
ps7_set_int_param ( "C_S_AXI_HP3_DATA_WIDTH",C_S_AXI_HP3_DATA_WIDTH );
ps7_set_int_param ( "C_M_AXI_GP0_THREAD_ID_WIDTH",C_M_AXI_GP0_THREAD_ID_WIDTH );
ps7_set_int_param ( "C_M_AXI_GP1_THREAD_ID_WIDTH",C_M_AXI_GP1_THREAD_ID_WIDTH );
ps7_set_int_param ( "C_NUM_F2P_INTR_INPUTS",C_NUM_F2P_INTR_INPUTS );
ps7_set_str_param ( "C_IRQ_F2P_MODE",C_IRQ_F2P_MODE );
ps7_set_int_param ( "C_DQ_WIDTH",C_DQ_WIDTH );
ps7_set_int_param ( "C_DQS_WIDTH",C_DQS_WIDTH );
ps7_set_int_param ( "C_DM_WIDTH",C_DM_WIDTH );
ps7_set_int_param ( "C_MIO_PRIMITIVE",C_MIO_PRIMITIVE );
ps7_set_int_param ( "C_TRACE_INTERNAL_WIDTH",C_TRACE_INTERNAL_WIDTH );
ps7_set_int_param ( "C_USE_AXI_NONSECURE",C_USE_AXI_NONSECURE );
ps7_set_int_param ( "C_USE_M_AXI_GP0",C_USE_M_AXI_GP0 );
ps7_set_int_param ( "C_USE_M_AXI_GP1",C_USE_M_AXI_GP1 );
ps7_set_int_param ( "C_USE_S_AXI_GP0",C_USE_S_AXI_GP0 );
ps7_set_int_param ( "C_USE_S_AXI_GP1",C_USE_S_AXI_GP1 );
ps7_set_int_param ( "C_USE_S_AXI_HP0",C_USE_S_AXI_HP0 );
ps7_set_int_param ( "C_USE_S_AXI_HP1",C_USE_S_AXI_HP1 );
ps7_set_int_param ( "C_USE_S_AXI_HP2",C_USE_S_AXI_HP2 );
ps7_set_int_param ( "C_USE_S_AXI_HP3",C_USE_S_AXI_HP3 );
ps7_set_int_param ( "C_USE_S_AXI_ACP",C_USE_S_AXI_ACP );
ps7_set_str_param ( "C_PS7_SI_REV",C_PS7_SI_REV );
ps7_set_str_param ( "C_FCLK_CLK0_BUF",C_FCLK_CLK0_BUF );
ps7_set_str_param ( "C_FCLK_CLK1_BUF",C_FCLK_CLK1_BUF );
ps7_set_str_param ( "C_FCLK_CLK2_BUF",C_FCLK_CLK2_BUF );
ps7_set_str_param ( "C_FCLK_CLK3_BUF",C_FCLK_CLK3_BUF );
ps7_set_str_param ( "C_PACKAGE_NAME",C_PACKAGE_NAME );
ps7_set_str_param ( "C_GP0_EN_MODIFIABLE_TXN",C_GP0_EN_MODIFIABLE_TXN );
ps7_set_str_param ( "C_GP1_EN_MODIFIABLE_TXN",C_GP1_EN_MODIFIABLE_TXN );
ps7_init_c_model();
end
initial
begin
FCLK_CLK0 = 1'b0;
end
always #(5.0) FCLK_CLK0 <= ~FCLK_CLK0;
always@(posedge FCLK_CLK0)
begin
ps7_set_ip_context(ip_name);
ps7_simulate_single_cycle_FCLK_CLK0();
end
endmodule

500
examples/.gen/sources_1/ip/zynqps/sim/zynqps.v Normal file
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@ -0,0 +1,500 @@
// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:processing_system7_vip:1.0
// IP Revision: 1
`timescale 1ns/1ps
module zynqps (
FCLK_CLK0,
FCLK_RESET0_N,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB
);
output FCLK_CLK0;
output FCLK_RESET0_N;
input [53 : 0] MIO;
input DDR_CAS_n;
input DDR_CKE;
input DDR_Clk_n;
input DDR_Clk;
input DDR_CS_n;
input DDR_DRSTB;
input DDR_ODT;
input DDR_RAS_n;
input DDR_WEB;
input [2 : 0] DDR_BankAddr;
input [14 : 0] DDR_Addr;
input DDR_VRN;
input DDR_VRP;
input [3 : 0] DDR_DM;
input [31 : 0] DDR_DQ;
input [3 : 0] DDR_DQS_n;
input [3 : 0] DDR_DQS;
input PS_SRSTB;
input PS_CLK;
input PS_PORB;
processing_system7_vip_v1_0_13 #(
.C_USE_M_AXI_GP0(0),
.C_USE_M_AXI_GP1(0),
.C_USE_S_AXI_ACP(0),
.C_USE_S_AXI_GP0(0),
.C_USE_S_AXI_GP1(0),
.C_USE_S_AXI_HP0(0),
.C_USE_S_AXI_HP1(0),
.C_USE_S_AXI_HP2(0),
.C_USE_S_AXI_HP3(0),
.C_S_AXI_HP0_DATA_WIDTH(64),
.C_S_AXI_HP1_DATA_WIDTH(64),
.C_S_AXI_HP2_DATA_WIDTH(64),
.C_S_AXI_HP3_DATA_WIDTH(64),
.C_HIGH_OCM_EN(0),
.C_FCLK_CLK0_FREQ(100.0),
.C_FCLK_CLK1_FREQ(10.0),
.C_FCLK_CLK2_FREQ(10.0),
.C_FCLK_CLK3_FREQ(10.0),
.C_M_AXI_GP0_ENABLE_STATIC_REMAP(0),
.C_M_AXI_GP1_ENABLE_STATIC_REMAP(0),
.C_M_AXI_GP0_THREAD_ID_WIDTH (12),
.C_M_AXI_GP1_THREAD_ID_WIDTH (12)
) inst (
.M_AXI_GP0_ARVALID(),
.M_AXI_GP0_AWVALID(),
.M_AXI_GP0_BREADY(),
.M_AXI_GP0_RREADY(),
.M_AXI_GP0_WLAST(),
.M_AXI_GP0_WVALID(),
.M_AXI_GP0_ARID(),
.M_AXI_GP0_AWID(),
.M_AXI_GP0_WID(),
.M_AXI_GP0_ARBURST(),
.M_AXI_GP0_ARLOCK(),
.M_AXI_GP0_ARSIZE(),
.M_AXI_GP0_AWBURST(),
.M_AXI_GP0_AWLOCK(),
.M_AXI_GP0_AWSIZE(),
.M_AXI_GP0_ARPROT(),
.M_AXI_GP0_AWPROT(),
.M_AXI_GP0_ARADDR(),
.M_AXI_GP0_AWADDR(),
.M_AXI_GP0_WDATA(),
.M_AXI_GP0_ARCACHE(),
.M_AXI_GP0_ARLEN(),
.M_AXI_GP0_ARQOS(),
.M_AXI_GP0_AWCACHE(),
.M_AXI_GP0_AWLEN(),
.M_AXI_GP0_AWQOS(),
.M_AXI_GP0_WSTRB(),
.M_AXI_GP0_ACLK(1'B0),
.M_AXI_GP0_ARREADY(1'B0),
.M_AXI_GP0_AWREADY(1'B0),
.M_AXI_GP0_BVALID(1'B0),
.M_AXI_GP0_RLAST(1'B0),
.M_AXI_GP0_RVALID(1'B0),
.M_AXI_GP0_WREADY(1'B0),
.M_AXI_GP0_BID(12'B0),
.M_AXI_GP0_RID(12'B0),
.M_AXI_GP0_BRESP(2'B0),
.M_AXI_GP0_RRESP(2'B0),
.M_AXI_GP0_RDATA(32'B0),
.M_AXI_GP1_ARVALID(),
.M_AXI_GP1_AWVALID(),
.M_AXI_GP1_BREADY(),
.M_AXI_GP1_RREADY(),
.M_AXI_GP1_WLAST(),
.M_AXI_GP1_WVALID(),
.M_AXI_GP1_ARID(),
.M_AXI_GP1_AWID(),
.M_AXI_GP1_WID(),
.M_AXI_GP1_ARBURST(),
.M_AXI_GP1_ARLOCK(),
.M_AXI_GP1_ARSIZE(),
.M_AXI_GP1_AWBURST(),
.M_AXI_GP1_AWLOCK(),
.M_AXI_GP1_AWSIZE(),
.M_AXI_GP1_ARPROT(),
.M_AXI_GP1_AWPROT(),
.M_AXI_GP1_ARADDR(),
.M_AXI_GP1_AWADDR(),
.M_AXI_GP1_WDATA(),
.M_AXI_GP1_ARCACHE(),
.M_AXI_GP1_ARLEN(),
.M_AXI_GP1_ARQOS(),
.M_AXI_GP1_AWCACHE(),
.M_AXI_GP1_AWLEN(),
.M_AXI_GP1_AWQOS(),
.M_AXI_GP1_WSTRB(),
.M_AXI_GP1_ACLK(1'B0),
.M_AXI_GP1_ARREADY(1'B0),
.M_AXI_GP1_AWREADY(1'B0),
.M_AXI_GP1_BVALID(1'B0),
.M_AXI_GP1_RLAST(1'B0),
.M_AXI_GP1_RVALID(1'B0),
.M_AXI_GP1_WREADY(1'B0),
.M_AXI_GP1_BID(12'B0),
.M_AXI_GP1_RID(12'B0),
.M_AXI_GP1_BRESP(2'B0),
.M_AXI_GP1_RRESP(2'B0),
.M_AXI_GP1_RDATA(32'B0),
.S_AXI_GP0_ARREADY(),
.S_AXI_GP0_AWREADY(),
.S_AXI_GP0_BVALID(),
.S_AXI_GP0_RLAST(),
.S_AXI_GP0_RVALID(),
.S_AXI_GP0_WREADY(),
.S_AXI_GP0_BRESP(),
.S_AXI_GP0_RRESP(),
.S_AXI_GP0_RDATA(),
.S_AXI_GP0_BID(),
.S_AXI_GP0_RID(),
.S_AXI_GP0_ACLK(1'B0),
.S_AXI_GP0_ARVALID(1'B0),
.S_AXI_GP0_AWVALID(1'B0),
.S_AXI_GP0_BREADY(1'B0),
.S_AXI_GP0_RREADY(1'B0),
.S_AXI_GP0_WLAST(1'B0),
.S_AXI_GP0_WVALID(1'B0),
.S_AXI_GP0_ARBURST(2'B0),
.S_AXI_GP0_ARLOCK(2'B0),
.S_AXI_GP0_ARSIZE(3'B0),
.S_AXI_GP0_AWBURST(2'B0),
.S_AXI_GP0_AWLOCK(2'B0),
.S_AXI_GP0_AWSIZE(3'B0),
.S_AXI_GP0_ARPROT(3'B0),
.S_AXI_GP0_AWPROT(3'B0),
.S_AXI_GP0_ARADDR(32'B0),
.S_AXI_GP0_AWADDR(32'B0),
.S_AXI_GP0_WDATA(32'B0),
.S_AXI_GP0_ARCACHE(4'B0),
.S_AXI_GP0_ARLEN(4'B0),
.S_AXI_GP0_ARQOS(4'B0),
.S_AXI_GP0_AWCACHE(4'B0),
.S_AXI_GP0_AWLEN(4'B0),
.S_AXI_GP0_AWQOS(4'B0),
.S_AXI_GP0_WSTRB(4'B0),
.S_AXI_GP0_ARID(6'B0),
.S_AXI_GP0_AWID(6'B0),
.S_AXI_GP0_WID(6'B0),
.S_AXI_GP1_ARREADY(),
.S_AXI_GP1_AWREADY(),
.S_AXI_GP1_BVALID(),
.S_AXI_GP1_RLAST(),
.S_AXI_GP1_RVALID(),
.S_AXI_GP1_WREADY(),
.S_AXI_GP1_BRESP(),
.S_AXI_GP1_RRESP(),
.S_AXI_GP1_RDATA(),
.S_AXI_GP1_BID(),
.S_AXI_GP1_RID(),
.S_AXI_GP1_ACLK(1'B0),
.S_AXI_GP1_ARVALID(1'B0),
.S_AXI_GP1_AWVALID(1'B0),
.S_AXI_GP1_BREADY(1'B0),
.S_AXI_GP1_RREADY(1'B0),
.S_AXI_GP1_WLAST(1'B0),
.S_AXI_GP1_WVALID(1'B0),
.S_AXI_GP1_ARBURST(2'B0),
.S_AXI_GP1_ARLOCK(2'B0),
.S_AXI_GP1_ARSIZE(3'B0),
.S_AXI_GP1_AWBURST(2'B0),
.S_AXI_GP1_AWLOCK(2'B0),
.S_AXI_GP1_AWSIZE(3'B0),
.S_AXI_GP1_ARPROT(3'B0),
.S_AXI_GP1_AWPROT(3'B0),
.S_AXI_GP1_ARADDR(32'B0),
.S_AXI_GP1_AWADDR(32'B0),
.S_AXI_GP1_WDATA(32'B0),
.S_AXI_GP1_ARCACHE(4'B0),
.S_AXI_GP1_ARLEN(4'B0),
.S_AXI_GP1_ARQOS(4'B0),
.S_AXI_GP1_AWCACHE(4'B0),
.S_AXI_GP1_AWLEN(4'B0),
.S_AXI_GP1_AWQOS(4'B0),
.S_AXI_GP1_WSTRB(4'B0),
.S_AXI_GP1_ARID(6'B0),
.S_AXI_GP1_AWID(6'B0),
.S_AXI_GP1_WID(6'B0),
.S_AXI_ACP_ARREADY(),
.S_AXI_ACP_AWREADY(),
.S_AXI_ACP_BVALID(),
.S_AXI_ACP_RLAST(),
.S_AXI_ACP_RVALID(),
.S_AXI_ACP_WREADY(),
.S_AXI_ACP_BRESP(),
.S_AXI_ACP_RRESP(),
.S_AXI_ACP_BID(),
.S_AXI_ACP_RID(),
.S_AXI_ACP_RDATA(),
.S_AXI_ACP_ACLK(1'B0),
.S_AXI_ACP_ARVALID(1'B0),
.S_AXI_ACP_AWVALID(1'B0),
.S_AXI_ACP_BREADY(1'B0),
.S_AXI_ACP_RREADY(1'B0),
.S_AXI_ACP_WLAST(1'B0),
.S_AXI_ACP_WVALID(1'B0),
.S_AXI_ACP_ARID(3'B0),
.S_AXI_ACP_ARPROT(3'B0),
.S_AXI_ACP_AWID(3'B0),
.S_AXI_ACP_AWPROT(3'B0),
.S_AXI_ACP_WID(3'B0),
.S_AXI_ACP_ARADDR(32'B0),
.S_AXI_ACP_AWADDR(32'B0),
.S_AXI_ACP_ARCACHE(4'B0),
.S_AXI_ACP_ARLEN(4'B0),
.S_AXI_ACP_ARQOS(4'B0),
.S_AXI_ACP_AWCACHE(4'B0),
.S_AXI_ACP_AWLEN(4'B0),
.S_AXI_ACP_AWQOS(4'B0),
.S_AXI_ACP_ARBURST(2'B0),
.S_AXI_ACP_ARLOCK(2'B0),
.S_AXI_ACP_ARSIZE(3'B0),
.S_AXI_ACP_AWBURST(2'B0),
.S_AXI_ACP_AWLOCK(2'B0),
.S_AXI_ACP_AWSIZE(3'B0),
.S_AXI_ACP_ARUSER(5'B0),
.S_AXI_ACP_AWUSER(5'B0),
.S_AXI_ACP_WDATA(64'B0),
.S_AXI_ACP_WSTRB(8'B0),
.S_AXI_HP0_ARREADY(),
.S_AXI_HP0_AWREADY(),
.S_AXI_HP0_BVALID(),
.S_AXI_HP0_RLAST(),
.S_AXI_HP0_RVALID(),
.S_AXI_HP0_WREADY(),
.S_AXI_HP0_BRESP(),
.S_AXI_HP0_RRESP(),
.S_AXI_HP0_BID(),
.S_AXI_HP0_RID(),
.S_AXI_HP0_RDATA(),
.S_AXI_HP0_ACLK(1'B0),
.S_AXI_HP0_ARVALID(1'B0),
.S_AXI_HP0_AWVALID(1'B0),
.S_AXI_HP0_BREADY(1'B0),
.S_AXI_HP0_RREADY(1'B0),
.S_AXI_HP0_WLAST(1'B0),
.S_AXI_HP0_WVALID(1'B0),
.S_AXI_HP0_ARBURST(2'B0),
.S_AXI_HP0_ARLOCK(2'B0),
.S_AXI_HP0_ARSIZE(3'B0),
.S_AXI_HP0_AWBURST(2'B0),
.S_AXI_HP0_AWLOCK(2'B0),
.S_AXI_HP0_AWSIZE(3'B0),
.S_AXI_HP0_ARPROT(3'B0),
.S_AXI_HP0_AWPROT(3'B0),
.S_AXI_HP0_ARADDR(32'B0),
.S_AXI_HP0_AWADDR(32'B0),
.S_AXI_HP0_ARCACHE(4'B0),
.S_AXI_HP0_ARLEN(4'B0),
.S_AXI_HP0_ARQOS(4'B0),
.S_AXI_HP0_AWCACHE(4'B0),
.S_AXI_HP0_AWLEN(4'B0),
.S_AXI_HP0_AWQOS(4'B0),
.S_AXI_HP0_ARID(6'B0),
.S_AXI_HP0_AWID(6'B0),
.S_AXI_HP0_WID(6'B0),
.S_AXI_HP0_WDATA(64'B0),
.S_AXI_HP0_WSTRB(8'B0),
.S_AXI_HP1_ARREADY(),
.S_AXI_HP1_AWREADY(),
.S_AXI_HP1_BVALID(),
.S_AXI_HP1_RLAST(),
.S_AXI_HP1_RVALID(),
.S_AXI_HP1_WREADY(),
.S_AXI_HP1_BRESP(),
.S_AXI_HP1_RRESP(),
.S_AXI_HP1_BID(),
.S_AXI_HP1_RID(),
.S_AXI_HP1_RDATA(),
.S_AXI_HP1_ACLK(1'B0),
.S_AXI_HP1_ARVALID(1'B0),
.S_AXI_HP1_AWVALID(1'B0),
.S_AXI_HP1_BREADY(1'B0),
.S_AXI_HP1_RREADY(1'B0),
.S_AXI_HP1_WLAST(1'B0),
.S_AXI_HP1_WVALID(1'B0),
.S_AXI_HP1_ARBURST(2'B0),
.S_AXI_HP1_ARLOCK(2'B0),
.S_AXI_HP1_ARSIZE(3'B0),
.S_AXI_HP1_AWBURST(2'B0),
.S_AXI_HP1_AWLOCK(2'B0),
.S_AXI_HP1_AWSIZE(3'B0),
.S_AXI_HP1_ARPROT(3'B0),
.S_AXI_HP1_AWPROT(3'B0),
.S_AXI_HP1_ARADDR(32'B0),
.S_AXI_HP1_AWADDR(32'B0),
.S_AXI_HP1_ARCACHE(4'B0),
.S_AXI_HP1_ARLEN(4'B0),
.S_AXI_HP1_ARQOS(4'B0),
.S_AXI_HP1_AWCACHE(4'B0),
.S_AXI_HP1_AWLEN(4'B0),
.S_AXI_HP1_AWQOS(4'B0),
.S_AXI_HP1_ARID(6'B0),
.S_AXI_HP1_AWID(6'B0),
.S_AXI_HP1_WID(6'B0),
.S_AXI_HP1_WDATA(64'B0),
.S_AXI_HP1_WSTRB(8'B0),
.S_AXI_HP2_ARREADY(),
.S_AXI_HP2_AWREADY(),
.S_AXI_HP2_BVALID(),
.S_AXI_HP2_RLAST(),
.S_AXI_HP2_RVALID(),
.S_AXI_HP2_WREADY(),
.S_AXI_HP2_BRESP(),
.S_AXI_HP2_RRESP(),
.S_AXI_HP2_BID(),
.S_AXI_HP2_RID(),
.S_AXI_HP2_RDATA(),
.S_AXI_HP2_ACLK(1'B0),
.S_AXI_HP2_ARVALID(1'B0),
.S_AXI_HP2_AWVALID(1'B0),
.S_AXI_HP2_BREADY(1'B0),
.S_AXI_HP2_RREADY(1'B0),
.S_AXI_HP2_WLAST(1'B0),
.S_AXI_HP2_WVALID(1'B0),
.S_AXI_HP2_ARBURST(2'B0),
.S_AXI_HP2_ARLOCK(2'B0),
.S_AXI_HP2_ARSIZE(3'B0),
.S_AXI_HP2_AWBURST(2'B0),
.S_AXI_HP2_AWLOCK(2'B0),
.S_AXI_HP2_AWSIZE(3'B0),
.S_AXI_HP2_ARPROT(3'B0),
.S_AXI_HP2_AWPROT(3'B0),
.S_AXI_HP2_ARADDR(32'B0),
.S_AXI_HP2_AWADDR(32'B0),
.S_AXI_HP2_ARCACHE(4'B0),
.S_AXI_HP2_ARLEN(4'B0),
.S_AXI_HP2_ARQOS(4'B0),
.S_AXI_HP2_AWCACHE(4'B0),
.S_AXI_HP2_AWLEN(4'B0),
.S_AXI_HP2_AWQOS(4'B0),
.S_AXI_HP2_ARID(6'B0),
.S_AXI_HP2_AWID(6'B0),
.S_AXI_HP2_WID(6'B0),
.S_AXI_HP2_WDATA(64'B0),
.S_AXI_HP2_WSTRB(8'B0),
.S_AXI_HP3_ARREADY(),
.S_AXI_HP3_AWREADY(),
.S_AXI_HP3_BVALID(),
.S_AXI_HP3_RLAST(),
.S_AXI_HP3_RVALID(),
.S_AXI_HP3_WREADY(),
.S_AXI_HP3_BRESP(),
.S_AXI_HP3_RRESP(),
.S_AXI_HP3_BID(),
.S_AXI_HP3_RID(),
.S_AXI_HP3_RDATA(),
.S_AXI_HP3_ACLK(1'B0),
.S_AXI_HP3_ARVALID(1'B0),
.S_AXI_HP3_AWVALID(1'B0),
.S_AXI_HP3_BREADY(1'B0),
.S_AXI_HP3_RREADY(1'B0),
.S_AXI_HP3_WLAST(1'B0),
.S_AXI_HP3_WVALID(1'B0),
.S_AXI_HP3_ARBURST(2'B0),
.S_AXI_HP3_ARLOCK(2'B0),
.S_AXI_HP3_ARSIZE(3'B0),
.S_AXI_HP3_AWBURST(2'B0),
.S_AXI_HP3_AWLOCK(2'B0),
.S_AXI_HP3_AWSIZE(3'B0),
.S_AXI_HP3_ARPROT(3'B0),
.S_AXI_HP3_AWPROT(3'B0),
.S_AXI_HP3_ARADDR(32'B0),
.S_AXI_HP3_AWADDR(32'B0),
.S_AXI_HP3_ARCACHE(4'B0),
.S_AXI_HP3_ARLEN(4'B0),
.S_AXI_HP3_ARQOS(4'B0),
.S_AXI_HP3_AWCACHE(4'B0),
.S_AXI_HP3_AWLEN(4'B0),
.S_AXI_HP3_AWQOS(4'B0),
.S_AXI_HP3_ARID(6'B0),
.S_AXI_HP3_AWID(6'B0),
.S_AXI_HP3_WID(6'B0),
.S_AXI_HP3_WDATA(64'B0),
.S_AXI_HP3_WSTRB(8'B0),
.FCLK_CLK0(FCLK_CLK0),
.FCLK_CLK1(),
.FCLK_CLK2(),
.FCLK_CLK3(),
.FCLK_RESET0_N(FCLK_RESET0_N),
.FCLK_RESET1_N(),
.FCLK_RESET2_N(),
.FCLK_RESET3_N(),
.IRQ_F2P(16'B0),
.PS_SRSTB(PS_SRSTB),
.PS_CLK(PS_CLK),
.PS_PORB(PS_PORB)
);
endmodule

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// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
#include "zynqps_sc.h"
#include "processing_system7_v5_5_tlm.h"
#include <map>
#include <string>
zynqps_sc::zynqps_sc(const sc_core::sc_module_name& nm) : sc_core::sc_module(nm), mp_impl(NULL)
{
// configure connectivity manager
xsc::utils::xsc_sim_manager::addInstance("zynqps", this);
// initialize module
xsc::common_cpp::properties model_param_props;
model_param_props.addLong("C_EN_EMIO_PJTAG", "0");
model_param_props.addLong("C_EN_EMIO_ENET0", "0");
model_param_props.addLong("C_EN_EMIO_ENET1", "0");
model_param_props.addLong("C_EN_EMIO_TRACE", "0");
model_param_props.addLong("C_INCLUDE_TRACE_BUFFER", "0");
model_param_props.addLong("C_TRACE_BUFFER_FIFO_SIZE", "128");
model_param_props.addLong("USE_TRACE_DATA_EDGE_DETECTOR", "0");
model_param_props.addLong("C_TRACE_PIPELINE_WIDTH", "8");
model_param_props.addLong("C_TRACE_BUFFER_CLOCK_DELAY", "12");
model_param_props.addLong("C_EMIO_GPIO_WIDTH", "64");
model_param_props.addLong("C_INCLUDE_ACP_TRANS_CHECK", "0");
model_param_props.addLong("C_USE_DEFAULT_ACP_USER_VAL", "0");
model_param_props.addLong("C_S_AXI_ACP_ARUSER_VAL", "31");
model_param_props.addLong("C_S_AXI_ACP_AWUSER_VAL", "31");
model_param_props.addLong("C_M_AXI_GP0_ID_WIDTH", "12");
model_param_props.addLong("C_M_AXI_GP0_ENABLE_STATIC_REMAP", "0");
model_param_props.addLong("C_M_AXI_GP1_ID_WIDTH", "12");
model_param_props.addLong("C_M_AXI_GP1_ENABLE_STATIC_REMAP", "0");
model_param_props.addLong("C_S_AXI_GP0_ID_WIDTH", "6");
model_param_props.addLong("C_S_AXI_GP1_ID_WIDTH", "6");
model_param_props.addLong("C_S_AXI_ACP_ID_WIDTH", "3");
model_param_props.addLong("C_S_AXI_HP0_ID_WIDTH", "6");
model_param_props.addLong("C_S_AXI_HP0_DATA_WIDTH", "64");
model_param_props.addLong("C_S_AXI_HP1_ID_WIDTH", "6");
model_param_props.addLong("C_S_AXI_HP1_DATA_WIDTH", "64");
model_param_props.addLong("C_S_AXI_HP2_ID_WIDTH", "6");
model_param_props.addLong("C_S_AXI_HP2_DATA_WIDTH", "64");
model_param_props.addLong("C_S_AXI_HP3_ID_WIDTH", "6");
model_param_props.addLong("C_S_AXI_HP3_DATA_WIDTH", "64");
model_param_props.addLong("C_M_AXI_GP0_THREAD_ID_WIDTH", "12");
model_param_props.addLong("C_M_AXI_GP1_THREAD_ID_WIDTH", "12");
model_param_props.addLong("C_NUM_F2P_INTR_INPUTS", "1");
model_param_props.addLong("C_DQ_WIDTH", "32");
model_param_props.addLong("C_DQS_WIDTH", "4");
model_param_props.addLong("C_DM_WIDTH", "4");
model_param_props.addLong("C_MIO_PRIMITIVE", "54");
model_param_props.addLong("C_TRACE_INTERNAL_WIDTH", "2");
model_param_props.addLong("C_USE_AXI_NONSECURE", "0");
model_param_props.addLong("C_USE_M_AXI_GP0", "0");
model_param_props.addLong("C_USE_M_AXI_GP1", "0");
model_param_props.addLong("C_USE_S_AXI_GP0", "0");
model_param_props.addLong("C_USE_S_AXI_GP1", "0");
model_param_props.addLong("C_USE_S_AXI_HP0", "0");
model_param_props.addLong("C_USE_S_AXI_HP1", "0");
model_param_props.addLong("C_USE_S_AXI_HP2", "0");
model_param_props.addLong("C_USE_S_AXI_HP3", "0");
model_param_props.addLong("C_USE_S_AXI_ACP", "0");
model_param_props.addLong("C_GP0_EN_MODIFIABLE_TXN", "1");
model_param_props.addLong("C_GP1_EN_MODIFIABLE_TXN", "1");
model_param_props.addString("C_IRQ_F2P_MODE", "DIRECT");
model_param_props.addString("C_PS7_SI_REV", "PRODUCTION");
model_param_props.addString("C_FCLK_CLK0_BUF", "TRUE");
model_param_props.addString("C_FCLK_CLK1_BUF", "FALSE");
model_param_props.addString("C_FCLK_CLK2_BUF", "FALSE");
model_param_props.addString("C_FCLK_CLK3_BUF", "FALSE");
model_param_props.addString("C_PACKAGE_NAME", "clg400");
model_param_props.addString("COMPONENT_NAME", "zynqps");
mp_impl = new processing_system7_v5_5_tlm("inst", model_param_props);
}
zynqps_sc::~zynqps_sc()
{
xsc::utils::xsc_sim_manager::clean();
delete mp_impl;
}

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#ifndef IP_ZYNQPS_SC_H_
#define IP_ZYNQPS_SC_H_
// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
#ifndef XTLM
#include "xtlm.h"
#endif
#ifndef SYSTEMC_INCLUDED
#include <systemc>
#endif
#if defined(_MSC_VER)
#define DllExport __declspec(dllexport)
#elif defined(__GNUC__)
#define DllExport __attribute__ ((visibility("default")))
#else
#define DllExport
#endif
class processing_system7_v5_5_tlm;
class DllExport zynqps_sc : public sc_core::sc_module
{
public:
zynqps_sc(const sc_core::sc_module_name& nm);
virtual ~zynqps_sc();
// module socket-to-socket AXI TLM interfaces
// module socket-to-socket TLM interfaces
protected:
processing_system7_v5_5_tlm* mp_impl;
private:
zynqps_sc(const zynqps_sc&);
const zynqps_sc& operator=(const zynqps_sc&);
};
#endif // IP_ZYNQPS_SC_H_

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// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
//------------------------------------------------------------------------------------
// Filename: zynqps_stub.sv
// Description: This HDL file is intended to be used with following simulators only:
//
// Vivado Simulator (XSim)
// Cadence Xcelium Simulator
// Aldec Riviera-PRO Simulator
//
//------------------------------------------------------------------------------------
`timescale 1ps/1ps
`ifdef XILINX_SIMULATOR
`ifndef XILINX_SIMULATOR_BITASBOOL
`define XILINX_SIMULATOR_BITASBOOL
typedef bit bit_as_bool;
`endif
(* SC_MODULE_EXPORT *)
module zynqps (
output bit_as_bool FCLK_CLK0,
output bit_as_bool FCLK_RESET0_N,
output bit [53 : 0] MIO,
output bit_as_bool DDR_CAS_n,
output bit_as_bool DDR_CKE,
output bit_as_bool DDR_Clk_n,
output bit_as_bool DDR_Clk,
output bit_as_bool DDR_CS_n,
output bit_as_bool DDR_DRSTB,
output bit_as_bool DDR_ODT,
output bit_as_bool DDR_RAS_n,
output bit_as_bool DDR_WEB,
output bit [2 : 0] DDR_BankAddr,
output bit [14 : 0] DDR_Addr,
output bit_as_bool DDR_VRN,
output bit_as_bool DDR_VRP,
output bit [3 : 0] DDR_DM,
output bit [31 : 0] DDR_DQ,
output bit [3 : 0] DDR_DQS_n,
output bit [3 : 0] DDR_DQS,
output bit_as_bool PS_SRSTB,
output bit_as_bool PS_CLK,
output bit_as_bool PS_PORB
);
endmodule
`endif
`ifdef XCELIUM
(* XMSC_MODULE_EXPORT *)
module zynqps (FCLK_CLK0,FCLK_RESET0_N,MIO,DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr,DDR_Addr,DDR_VRN,DDR_VRP,DDR_DM,DDR_DQ,DDR_DQS_n,DDR_DQS,PS_SRSTB,PS_CLK,PS_PORB)
(* integer foreign = "SystemC";
*);
output wire FCLK_CLK0;
output wire FCLK_RESET0_N;
inout wire [53 : 0] MIO;
inout wire DDR_CAS_n;
inout wire DDR_CKE;
inout wire DDR_Clk_n;
inout wire DDR_Clk;
inout wire DDR_CS_n;
inout wire DDR_DRSTB;
inout wire DDR_ODT;
inout wire DDR_RAS_n;
inout wire DDR_WEB;
inout wire [2 : 0] DDR_BankAddr;
inout wire [14 : 0] DDR_Addr;
inout wire DDR_VRN;
inout wire DDR_VRP;
inout wire [3 : 0] DDR_DM;
inout wire [31 : 0] DDR_DQ;
inout wire [3 : 0] DDR_DQS_n;
inout wire [3 : 0] DDR_DQS;
inout wire PS_SRSTB;
inout wire PS_CLK;
inout wire PS_PORB;
endmodule
`endif
`ifdef RIVIERA
(* SC_MODULE_EXPORT *)
module zynqps (FCLK_CLK0,FCLK_RESET0_N,MIO,DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr,DDR_Addr,DDR_VRN,DDR_VRP,DDR_DM,DDR_DQ,DDR_DQS_n,DDR_DQS,PS_SRSTB,PS_CLK,PS_PORB)
output wire FCLK_CLK0;
output wire FCLK_RESET0_N;
inout wire [53 : 0] MIO;
inout wire DDR_CAS_n;
inout wire DDR_CKE;
inout wire DDR_Clk_n;
inout wire DDR_Clk;
inout wire DDR_CS_n;
inout wire DDR_DRSTB;
inout wire DDR_ODT;
inout wire DDR_RAS_n;
inout wire DDR_WEB;
inout wire [2 : 0] DDR_BankAddr;
inout wire [14 : 0] DDR_Addr;
inout wire DDR_VRN;
inout wire DDR_VRP;
inout wire [3 : 0] DDR_DM;
inout wire [31 : 0] DDR_DQ;
inout wire [3 : 0] DDR_DQS_n;
inout wire [3 : 0] DDR_DQS;
inout wire PS_SRSTB;
inout wire PS_CLK;
inout wire PS_PORB;
endmodule
`endif