501 lines
13 KiB
Verilog
501 lines
13 KiB
Verilog
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// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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// DO NOT MODIFY THIS FILE.
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// IP VLNV: xilinx.com:ip:processing_system7_vip:1.0
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// IP Revision: 1
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`timescale 1ns/1ps
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module zynqps (
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FCLK_CLK0,
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FCLK_RESET0_N,
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MIO,
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DDR_CAS_n,
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DDR_CKE,
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DDR_Clk_n,
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DDR_Clk,
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DDR_CS_n,
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DDR_DRSTB,
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DDR_ODT,
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DDR_RAS_n,
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DDR_WEB,
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DDR_BankAddr,
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DDR_Addr,
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DDR_VRN,
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DDR_VRP,
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DDR_DM,
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DDR_DQ,
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DDR_DQS_n,
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DDR_DQS,
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PS_SRSTB,
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PS_CLK,
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PS_PORB
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);
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output FCLK_CLK0;
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output FCLK_RESET0_N;
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input [53 : 0] MIO;
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input DDR_CAS_n;
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input DDR_CKE;
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input DDR_Clk_n;
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input DDR_Clk;
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input DDR_CS_n;
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input DDR_DRSTB;
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input DDR_ODT;
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input DDR_RAS_n;
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input DDR_WEB;
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input [2 : 0] DDR_BankAddr;
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input [14 : 0] DDR_Addr;
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input DDR_VRN;
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input DDR_VRP;
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input [3 : 0] DDR_DM;
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input [31 : 0] DDR_DQ;
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input [3 : 0] DDR_DQS_n;
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input [3 : 0] DDR_DQS;
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input PS_SRSTB;
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input PS_CLK;
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input PS_PORB;
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processing_system7_vip_v1_0_13 #(
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.C_USE_M_AXI_GP0(0),
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.C_USE_M_AXI_GP1(0),
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.C_USE_S_AXI_ACP(0),
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.C_USE_S_AXI_GP0(0),
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.C_USE_S_AXI_GP1(0),
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.C_USE_S_AXI_HP0(0),
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.C_USE_S_AXI_HP1(0),
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.C_USE_S_AXI_HP2(0),
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.C_USE_S_AXI_HP3(0),
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.C_S_AXI_HP0_DATA_WIDTH(64),
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.C_S_AXI_HP1_DATA_WIDTH(64),
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.C_S_AXI_HP2_DATA_WIDTH(64),
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.C_S_AXI_HP3_DATA_WIDTH(64),
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.C_HIGH_OCM_EN(0),
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.C_FCLK_CLK0_FREQ(100.0),
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.C_FCLK_CLK1_FREQ(10.0),
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.C_FCLK_CLK2_FREQ(10.0),
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.C_FCLK_CLK3_FREQ(10.0),
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.C_M_AXI_GP0_ENABLE_STATIC_REMAP(0),
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.C_M_AXI_GP1_ENABLE_STATIC_REMAP(0),
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.C_M_AXI_GP0_THREAD_ID_WIDTH (12),
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.C_M_AXI_GP1_THREAD_ID_WIDTH (12)
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) inst (
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.M_AXI_GP0_ARVALID(),
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.M_AXI_GP0_AWVALID(),
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.M_AXI_GP0_BREADY(),
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.M_AXI_GP0_RREADY(),
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.M_AXI_GP0_WLAST(),
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.M_AXI_GP0_WVALID(),
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.M_AXI_GP0_ARID(),
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.M_AXI_GP0_AWID(),
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.M_AXI_GP0_WID(),
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.M_AXI_GP0_ARBURST(),
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.M_AXI_GP0_ARLOCK(),
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.M_AXI_GP0_ARSIZE(),
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.M_AXI_GP0_AWBURST(),
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.M_AXI_GP0_AWLOCK(),
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.M_AXI_GP0_AWSIZE(),
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.M_AXI_GP0_ARPROT(),
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.M_AXI_GP0_AWPROT(),
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.M_AXI_GP0_ARADDR(),
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.M_AXI_GP0_AWADDR(),
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.M_AXI_GP0_WDATA(),
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.M_AXI_GP0_ARCACHE(),
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.M_AXI_GP0_ARLEN(),
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.M_AXI_GP0_ARQOS(),
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.M_AXI_GP0_AWCACHE(),
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.M_AXI_GP0_AWLEN(),
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.M_AXI_GP0_AWQOS(),
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.M_AXI_GP0_WSTRB(),
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.M_AXI_GP0_ACLK(1'B0),
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.M_AXI_GP0_ARREADY(1'B0),
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.M_AXI_GP0_AWREADY(1'B0),
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.M_AXI_GP0_BVALID(1'B0),
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.M_AXI_GP0_RLAST(1'B0),
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.M_AXI_GP0_RVALID(1'B0),
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.M_AXI_GP0_WREADY(1'B0),
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.M_AXI_GP0_BID(12'B0),
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.M_AXI_GP0_RID(12'B0),
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.M_AXI_GP0_BRESP(2'B0),
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.M_AXI_GP0_RRESP(2'B0),
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.M_AXI_GP0_RDATA(32'B0),
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.M_AXI_GP1_ARVALID(),
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.M_AXI_GP1_AWVALID(),
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.M_AXI_GP1_BREADY(),
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.M_AXI_GP1_RREADY(),
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.M_AXI_GP1_WLAST(),
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.M_AXI_GP1_WVALID(),
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.M_AXI_GP1_ARID(),
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.M_AXI_GP1_AWID(),
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.M_AXI_GP1_WID(),
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.M_AXI_GP1_ARBURST(),
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.M_AXI_GP1_ARLOCK(),
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.M_AXI_GP1_ARSIZE(),
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.M_AXI_GP1_AWBURST(),
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.M_AXI_GP1_AWLOCK(),
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.M_AXI_GP1_AWSIZE(),
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.M_AXI_GP1_ARPROT(),
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.M_AXI_GP1_AWPROT(),
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.M_AXI_GP1_ARADDR(),
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.M_AXI_GP1_AWADDR(),
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.M_AXI_GP1_WDATA(),
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.M_AXI_GP1_ARCACHE(),
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.M_AXI_GP1_ARLEN(),
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.M_AXI_GP1_ARQOS(),
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.M_AXI_GP1_AWCACHE(),
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.M_AXI_GP1_AWLEN(),
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.M_AXI_GP1_AWQOS(),
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.M_AXI_GP1_WSTRB(),
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.M_AXI_GP1_ACLK(1'B0),
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.M_AXI_GP1_ARREADY(1'B0),
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.M_AXI_GP1_AWREADY(1'B0),
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.M_AXI_GP1_BVALID(1'B0),
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.M_AXI_GP1_RLAST(1'B0),
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.M_AXI_GP1_RVALID(1'B0),
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.M_AXI_GP1_WREADY(1'B0),
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.M_AXI_GP1_BID(12'B0),
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.M_AXI_GP1_RID(12'B0),
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.M_AXI_GP1_BRESP(2'B0),
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.M_AXI_GP1_RRESP(2'B0),
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.M_AXI_GP1_RDATA(32'B0),
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.S_AXI_GP0_ARREADY(),
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.S_AXI_GP0_AWREADY(),
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.S_AXI_GP0_BVALID(),
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.S_AXI_GP0_RLAST(),
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.S_AXI_GP0_RVALID(),
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.S_AXI_GP0_WREADY(),
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.S_AXI_GP0_BRESP(),
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.S_AXI_GP0_RRESP(),
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.S_AXI_GP0_RDATA(),
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.S_AXI_GP0_BID(),
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.S_AXI_GP0_RID(),
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.S_AXI_GP0_ACLK(1'B0),
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.S_AXI_GP0_ARVALID(1'B0),
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.S_AXI_GP0_AWVALID(1'B0),
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.S_AXI_GP0_BREADY(1'B0),
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.S_AXI_GP0_RREADY(1'B0),
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.S_AXI_GP0_WLAST(1'B0),
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.S_AXI_GP0_WVALID(1'B0),
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.S_AXI_GP0_ARBURST(2'B0),
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.S_AXI_GP0_ARLOCK(2'B0),
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.S_AXI_GP0_ARSIZE(3'B0),
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.S_AXI_GP0_AWBURST(2'B0),
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.S_AXI_GP0_AWLOCK(2'B0),
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.S_AXI_GP0_AWSIZE(3'B0),
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.S_AXI_GP0_ARPROT(3'B0),
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.S_AXI_GP0_AWPROT(3'B0),
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.S_AXI_GP0_ARADDR(32'B0),
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.S_AXI_GP0_AWADDR(32'B0),
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.S_AXI_GP0_WDATA(32'B0),
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.S_AXI_GP0_ARCACHE(4'B0),
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.S_AXI_GP0_ARLEN(4'B0),
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.S_AXI_GP0_ARQOS(4'B0),
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.S_AXI_GP0_AWCACHE(4'B0),
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.S_AXI_GP0_AWLEN(4'B0),
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.S_AXI_GP0_AWQOS(4'B0),
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.S_AXI_GP0_WSTRB(4'B0),
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.S_AXI_GP0_ARID(6'B0),
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.S_AXI_GP0_AWID(6'B0),
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.S_AXI_GP0_WID(6'B0),
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.S_AXI_GP1_ARREADY(),
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.S_AXI_GP1_AWREADY(),
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.S_AXI_GP1_BVALID(),
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.S_AXI_GP1_RLAST(),
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.S_AXI_GP1_RVALID(),
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.S_AXI_GP1_WREADY(),
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.S_AXI_GP1_BRESP(),
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.S_AXI_GP1_RRESP(),
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.S_AXI_GP1_RDATA(),
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.S_AXI_GP1_BID(),
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.S_AXI_GP1_RID(),
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.S_AXI_GP1_ACLK(1'B0),
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.S_AXI_GP1_ARVALID(1'B0),
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.S_AXI_GP1_AWVALID(1'B0),
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.S_AXI_GP1_BREADY(1'B0),
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.S_AXI_GP1_RREADY(1'B0),
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.S_AXI_GP1_WLAST(1'B0),
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.S_AXI_GP1_WVALID(1'B0),
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.S_AXI_GP1_ARBURST(2'B0),
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.S_AXI_GP1_ARLOCK(2'B0),
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.S_AXI_GP1_ARSIZE(3'B0),
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.S_AXI_GP1_AWBURST(2'B0),
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.S_AXI_GP1_AWLOCK(2'B0),
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.S_AXI_GP1_AWSIZE(3'B0),
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.S_AXI_GP1_ARPROT(3'B0),
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.S_AXI_GP1_AWPROT(3'B0),
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.S_AXI_GP1_ARADDR(32'B0),
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.S_AXI_GP1_AWADDR(32'B0),
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.S_AXI_GP1_WDATA(32'B0),
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.S_AXI_GP1_ARCACHE(4'B0),
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.S_AXI_GP1_ARLEN(4'B0),
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.S_AXI_GP1_ARQOS(4'B0),
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.S_AXI_GP1_AWCACHE(4'B0),
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.S_AXI_GP1_AWLEN(4'B0),
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.S_AXI_GP1_AWQOS(4'B0),
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.S_AXI_GP1_WSTRB(4'B0),
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.S_AXI_GP1_ARID(6'B0),
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.S_AXI_GP1_AWID(6'B0),
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.S_AXI_GP1_WID(6'B0),
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.S_AXI_ACP_ARREADY(),
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.S_AXI_ACP_AWREADY(),
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.S_AXI_ACP_BVALID(),
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.S_AXI_ACP_RLAST(),
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.S_AXI_ACP_RVALID(),
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.S_AXI_ACP_WREADY(),
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.S_AXI_ACP_BRESP(),
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.S_AXI_ACP_RRESP(),
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.S_AXI_ACP_BID(),
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.S_AXI_ACP_RID(),
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.S_AXI_ACP_RDATA(),
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.S_AXI_ACP_ACLK(1'B0),
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.S_AXI_ACP_ARVALID(1'B0),
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.S_AXI_ACP_AWVALID(1'B0),
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.S_AXI_ACP_BREADY(1'B0),
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.S_AXI_ACP_RREADY(1'B0),
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.S_AXI_ACP_WLAST(1'B0),
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.S_AXI_ACP_WVALID(1'B0),
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.S_AXI_ACP_ARID(3'B0),
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.S_AXI_ACP_ARPROT(3'B0),
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.S_AXI_ACP_AWID(3'B0),
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.S_AXI_ACP_AWPROT(3'B0),
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.S_AXI_ACP_WID(3'B0),
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.S_AXI_ACP_ARADDR(32'B0),
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.S_AXI_ACP_AWADDR(32'B0),
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.S_AXI_ACP_ARCACHE(4'B0),
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.S_AXI_ACP_ARLEN(4'B0),
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.S_AXI_ACP_ARQOS(4'B0),
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.S_AXI_ACP_AWCACHE(4'B0),
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.S_AXI_ACP_AWLEN(4'B0),
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.S_AXI_ACP_AWQOS(4'B0),
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.S_AXI_ACP_ARBURST(2'B0),
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.S_AXI_ACP_ARLOCK(2'B0),
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.S_AXI_ACP_ARSIZE(3'B0),
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.S_AXI_ACP_AWBURST(2'B0),
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.S_AXI_ACP_AWLOCK(2'B0),
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.S_AXI_ACP_AWSIZE(3'B0),
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.S_AXI_ACP_ARUSER(5'B0),
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.S_AXI_ACP_AWUSER(5'B0),
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.S_AXI_ACP_WDATA(64'B0),
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.S_AXI_ACP_WSTRB(8'B0),
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.S_AXI_HP0_ARREADY(),
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.S_AXI_HP0_AWREADY(),
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.S_AXI_HP0_BVALID(),
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.S_AXI_HP0_RLAST(),
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.S_AXI_HP0_RVALID(),
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.S_AXI_HP0_WREADY(),
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.S_AXI_HP0_BRESP(),
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.S_AXI_HP0_RRESP(),
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.S_AXI_HP0_BID(),
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.S_AXI_HP0_RID(),
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.S_AXI_HP0_RDATA(),
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.S_AXI_HP0_ACLK(1'B0),
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.S_AXI_HP0_ARVALID(1'B0),
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.S_AXI_HP0_AWVALID(1'B0),
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.S_AXI_HP0_BREADY(1'B0),
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.S_AXI_HP0_RREADY(1'B0),
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.S_AXI_HP0_WLAST(1'B0),
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.S_AXI_HP0_WVALID(1'B0),
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.S_AXI_HP0_ARBURST(2'B0),
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.S_AXI_HP0_ARLOCK(2'B0),
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.S_AXI_HP0_ARSIZE(3'B0),
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.S_AXI_HP0_AWBURST(2'B0),
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.S_AXI_HP0_AWLOCK(2'B0),
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.S_AXI_HP0_AWSIZE(3'B0),
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.S_AXI_HP0_ARPROT(3'B0),
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.S_AXI_HP0_AWPROT(3'B0),
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.S_AXI_HP0_ARADDR(32'B0),
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.S_AXI_HP0_AWADDR(32'B0),
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.S_AXI_HP0_ARCACHE(4'B0),
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.S_AXI_HP0_ARLEN(4'B0),
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.S_AXI_HP0_ARQOS(4'B0),
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.S_AXI_HP0_AWCACHE(4'B0),
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.S_AXI_HP0_AWLEN(4'B0),
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.S_AXI_HP0_AWQOS(4'B0),
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.S_AXI_HP0_ARID(6'B0),
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.S_AXI_HP0_AWID(6'B0),
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.S_AXI_HP0_WID(6'B0),
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.S_AXI_HP0_WDATA(64'B0),
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.S_AXI_HP0_WSTRB(8'B0),
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.S_AXI_HP1_ARREADY(),
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.S_AXI_HP1_AWREADY(),
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.S_AXI_HP1_BVALID(),
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.S_AXI_HP1_RLAST(),
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.S_AXI_HP1_RVALID(),
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.S_AXI_HP1_WREADY(),
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.S_AXI_HP1_BRESP(),
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.S_AXI_HP1_RRESP(),
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.S_AXI_HP1_BID(),
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.S_AXI_HP1_RID(),
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.S_AXI_HP1_RDATA(),
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.S_AXI_HP1_ACLK(1'B0),
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.S_AXI_HP1_ARVALID(1'B0),
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.S_AXI_HP1_AWVALID(1'B0),
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.S_AXI_HP1_BREADY(1'B0),
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.S_AXI_HP1_RREADY(1'B0),
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.S_AXI_HP1_WLAST(1'B0),
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.S_AXI_HP1_WVALID(1'B0),
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.S_AXI_HP1_ARBURST(2'B0),
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.S_AXI_HP1_ARLOCK(2'B0),
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.S_AXI_HP1_ARSIZE(3'B0),
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.S_AXI_HP1_AWBURST(2'B0),
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.S_AXI_HP1_AWLOCK(2'B0),
|
|
.S_AXI_HP1_AWSIZE(3'B0),
|
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.S_AXI_HP1_ARPROT(3'B0),
|
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.S_AXI_HP1_AWPROT(3'B0),
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|
.S_AXI_HP1_ARADDR(32'B0),
|
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.S_AXI_HP1_AWADDR(32'B0),
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|
.S_AXI_HP1_ARCACHE(4'B0),
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|
.S_AXI_HP1_ARLEN(4'B0),
|
|
.S_AXI_HP1_ARQOS(4'B0),
|
|
.S_AXI_HP1_AWCACHE(4'B0),
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|
.S_AXI_HP1_AWLEN(4'B0),
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|
.S_AXI_HP1_AWQOS(4'B0),
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|
.S_AXI_HP1_ARID(6'B0),
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|
.S_AXI_HP1_AWID(6'B0),
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|
.S_AXI_HP1_WID(6'B0),
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|
.S_AXI_HP1_WDATA(64'B0),
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|
.S_AXI_HP1_WSTRB(8'B0),
|
|
.S_AXI_HP2_ARREADY(),
|
|
.S_AXI_HP2_AWREADY(),
|
|
.S_AXI_HP2_BVALID(),
|
|
.S_AXI_HP2_RLAST(),
|
|
.S_AXI_HP2_RVALID(),
|
|
.S_AXI_HP2_WREADY(),
|
|
.S_AXI_HP2_BRESP(),
|
|
.S_AXI_HP2_RRESP(),
|
|
.S_AXI_HP2_BID(),
|
|
.S_AXI_HP2_RID(),
|
|
.S_AXI_HP2_RDATA(),
|
|
.S_AXI_HP2_ACLK(1'B0),
|
|
.S_AXI_HP2_ARVALID(1'B0),
|
|
.S_AXI_HP2_AWVALID(1'B0),
|
|
.S_AXI_HP2_BREADY(1'B0),
|
|
.S_AXI_HP2_RREADY(1'B0),
|
|
.S_AXI_HP2_WLAST(1'B0),
|
|
.S_AXI_HP2_WVALID(1'B0),
|
|
.S_AXI_HP2_ARBURST(2'B0),
|
|
.S_AXI_HP2_ARLOCK(2'B0),
|
|
.S_AXI_HP2_ARSIZE(3'B0),
|
|
.S_AXI_HP2_AWBURST(2'B0),
|
|
.S_AXI_HP2_AWLOCK(2'B0),
|
|
.S_AXI_HP2_AWSIZE(3'B0),
|
|
.S_AXI_HP2_ARPROT(3'B0),
|
|
.S_AXI_HP2_AWPROT(3'B0),
|
|
.S_AXI_HP2_ARADDR(32'B0),
|
|
.S_AXI_HP2_AWADDR(32'B0),
|
|
.S_AXI_HP2_ARCACHE(4'B0),
|
|
.S_AXI_HP2_ARLEN(4'B0),
|
|
.S_AXI_HP2_ARQOS(4'B0),
|
|
.S_AXI_HP2_AWCACHE(4'B0),
|
|
.S_AXI_HP2_AWLEN(4'B0),
|
|
.S_AXI_HP2_AWQOS(4'B0),
|
|
.S_AXI_HP2_ARID(6'B0),
|
|
.S_AXI_HP2_AWID(6'B0),
|
|
.S_AXI_HP2_WID(6'B0),
|
|
.S_AXI_HP2_WDATA(64'B0),
|
|
.S_AXI_HP2_WSTRB(8'B0),
|
|
.S_AXI_HP3_ARREADY(),
|
|
.S_AXI_HP3_AWREADY(),
|
|
.S_AXI_HP3_BVALID(),
|
|
.S_AXI_HP3_RLAST(),
|
|
.S_AXI_HP3_RVALID(),
|
|
.S_AXI_HP3_WREADY(),
|
|
.S_AXI_HP3_BRESP(),
|
|
.S_AXI_HP3_RRESP(),
|
|
.S_AXI_HP3_BID(),
|
|
.S_AXI_HP3_RID(),
|
|
.S_AXI_HP3_RDATA(),
|
|
.S_AXI_HP3_ACLK(1'B0),
|
|
.S_AXI_HP3_ARVALID(1'B0),
|
|
.S_AXI_HP3_AWVALID(1'B0),
|
|
.S_AXI_HP3_BREADY(1'B0),
|
|
.S_AXI_HP3_RREADY(1'B0),
|
|
.S_AXI_HP3_WLAST(1'B0),
|
|
.S_AXI_HP3_WVALID(1'B0),
|
|
.S_AXI_HP3_ARBURST(2'B0),
|
|
.S_AXI_HP3_ARLOCK(2'B0),
|
|
.S_AXI_HP3_ARSIZE(3'B0),
|
|
.S_AXI_HP3_AWBURST(2'B0),
|
|
.S_AXI_HP3_AWLOCK(2'B0),
|
|
.S_AXI_HP3_AWSIZE(3'B0),
|
|
.S_AXI_HP3_ARPROT(3'B0),
|
|
.S_AXI_HP3_AWPROT(3'B0),
|
|
.S_AXI_HP3_ARADDR(32'B0),
|
|
.S_AXI_HP3_AWADDR(32'B0),
|
|
.S_AXI_HP3_ARCACHE(4'B0),
|
|
.S_AXI_HP3_ARLEN(4'B0),
|
|
.S_AXI_HP3_ARQOS(4'B0),
|
|
.S_AXI_HP3_AWCACHE(4'B0),
|
|
.S_AXI_HP3_AWLEN(4'B0),
|
|
.S_AXI_HP3_AWQOS(4'B0),
|
|
.S_AXI_HP3_ARID(6'B0),
|
|
.S_AXI_HP3_AWID(6'B0),
|
|
.S_AXI_HP3_WID(6'B0),
|
|
.S_AXI_HP3_WDATA(64'B0),
|
|
.S_AXI_HP3_WSTRB(8'B0),
|
|
.FCLK_CLK0(FCLK_CLK0),
|
|
|
|
.FCLK_CLK1(),
|
|
|
|
.FCLK_CLK2(),
|
|
|
|
.FCLK_CLK3(),
|
|
.FCLK_RESET0_N(FCLK_RESET0_N),
|
|
.FCLK_RESET1_N(),
|
|
.FCLK_RESET2_N(),
|
|
.FCLK_RESET3_N(),
|
|
.IRQ_F2P(16'B0),
|
|
.PS_SRSTB(PS_SRSTB),
|
|
.PS_CLK(PS_CLK),
|
|
.PS_PORB(PS_PORB)
|
|
);
|
|
endmodule
|