Added ghdl simulation toolchain

Signed-off-by: Joppe Blondel <joppe@blondel.nl>

examples/formal/.gitignore

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+OUT
+BUILD

examples/formal/RTL/counter.vhd

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+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity counter is
+    generic (
+        -- Formal generic is used to embed formal validation stuff
+        formal          : boolean := false;
+        -- Data width
+        width           : integer := 16;
+        -- Max count
+        mxcnt           : integer := 256
+    );
+    port (
+        ACLK            : in std_logic;
+        ARESETN         : in std_logic;
+        cnt             : out std_logic_vector(width-1 downto 0)
+    );
+end entity;
+
+architecture behav of counter is
+    signal icnt : unsigned (width-1 downto 0);
+begin
+
+    cnt <= std_logic_vector(icnt);
+
+    process(ACLK, ARESETN)
+    begin
+        if ARESETN='0' then
+            icnt <= (others=>'0');
+        elsif rising_edge(ACLK) then
+            if icnt<mxcnt then
+                icnt <= icnt + 1;
+            else 
+                icnt <= (others=>'0');
+            end if;
+        end if;
+    end process;
+
+end architecture;

examples/formal/SIM/tb_counter.vhd

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+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity tb_counter is
+end entity;
+
+architecture behav of tb_counter is
+
+    component counter is
+        generic (
+            formal          : boolean := false;
+            width           : integer := 16;
+            mxcnt           : integer := 256
+        );
+        port (
+            ACLK            : in std_logic;
+            ARESETN         : in std_logic;
+            cnt             : out std_logic_vector(width-1 downto 0)
+        );
+    end component;
+
+    signal ACLK, ARESETN : std_logic := '0';
+    signal cnt : std_logic_vector(15 downto 0);
+
+begin
+
+    ACLK <= not ACLK after 10 ns;
+    ARESETN <= '1' after 50 ns;
+
+    process
+    begin
+        wait for 2 us;
+        report "END OF SIMULATION" severity failure;
+    end process;
+
+    c_counter : component counter
+        generic map(
+            formal => false,
+            width => cnt'length,
+            mxcnt => 5
+        ) port map (
+            ACLK => ACLK,
+            ARESETN => ARESETN,
+            cnt => cnt
+        );
+        
+end architecture;

examples/formal/project.cfg

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+[project]
+name                = formal_project
+version             = 0.1
+out_dir             = OUT
+build_dir           = BUILD
+
+[server]
+hostname            = localhost
+port                = 2020
+privkey             = /home/joppe/.ssh/id_rsa
+pubkey              = /home/joppe/.ssh/id_rsa.pub
+
+# ######################################
+# Basic VHDL simulation with GHDL
+[target.sim]
+toolchain           = ghdl
+
+# Toolchain settings
+toplevel            = tb_counter
+runtime             = all
+#ghdla_opts         = 
+#ghdle_opts         = 
+#ghdlr_opts         = 
+
+# Fileset
+files_vhdl          = RTL/counter.vhd 
+                      SIM/tb_counter.vhd
+# ######################################