New project structure

Rewrite of all functions

Signed-off-by: Jojojoppe <joppe@blondel.nl>
This commit is contained in:
2022-09-03 21:52:29 +02:00
parent cbcea361bb
commit 162aaf47a0
31 changed files with 209 additions and 2111 deletions

19
project.cfg Normal file
View File

@ -0,0 +1,19 @@
[project]
name = testproject
version = 0.1
out_dir = OUT
build_dir = BUILD
[target:default]
family = spartan6
device = xc6slx9
package = tqg144
speedgrade = -2
toolchain = ISE
[sources:default]
target = default
toplevel = toplevel
src_vhdl = RTL/toplevel.vhd
src_verilog =
src_sysverilog =