Added isim target

Signed-off-by: Joppe Blondel <joppe@blondel.nl>

examples/spartan6/project.cfg

@@ -10,6 +10,8 @@ port                = 2020
 privkey             = /home/joppe/.ssh/id_rsa
 pubkey              = /home/joppe/.ssh/id_rsa.pub
 
+# ######################################
+# Basic synthesis
 [target.synth]
 toolchain           = ISE
 
@@ -29,5 +31,43 @@ toplevel            = toplevel
 
 # Fileset
 files_vhdl          = RTL/toplevel.vhd
-#files_verilog       =
-files_con           = CON/toplevel.ucf
+#files_verilog      =
+files_con           = CON/toplevel.ucf
+# ######################################
+
+# ######################################
+# Behavioural simulation
+[target.sim]
+toolchain           = isim
+
+# Toolchain settings
+toplevel            = tb_toplevel
+vcdlevels           = 20
+runtime             = all
+#fuse_opts           =
+#isim_opts           =
+
+# Fileset
+files_vhdl          = RTL/toplevel.vhd
+                      SIM/tb_toplevel.vhd
+#files_verilog      =
+# ######################################
+
+# ######################################
+# Post synthesis simulation (synth must have ran first)
+[target.psim]
+toolchain           = isim
+
+# Toolchain settings
+toplevel            = tb_toplevel
+vcdlevels           = 20
+runtime             = all
+fuse_opts           = --maxdelay work.glbl
+isim_opts           = -sdfmax /tb_toplevel/c_toplevel=%%D%%/OUT/synth/synth.sdf
+# %%D%% is replaced with the top directory of the project
+
+# Fileset
+files_vhdl          = SIM/tb_toplevel.vhd
+files_verilog       = OUT/synth/synth.v
+files_other         = OUT/synth/synth.sdf
+# ######################################