77 lines
1.7 KiB
Verilog
77 lines
1.7 KiB
Verilog
`timescale 1ns/1ps
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module soclet #(
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parameter memfile = "",
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parameter memsize = 8192,
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parameter sim = 1'b0
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)(
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input wire i_clk,
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input wire i_rst,
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input wire [31:0] i_GPI_A,
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input wire [31:0] i_GPI_B,
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input wire [31:0] i_GPI_C,
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input wire [31:0] i_GPI_D,
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output wire [31:0] o_GPO_A,
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output wire [31:0] o_GPO_B,
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output wire [31:0] o_GPO_C,
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output wire [31:0] o_GPO_D
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);
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wire [31:0] wb_adr;
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wire [31:0] wb_dat;
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wire [31:0] wb_rdt;
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wire [3:0] wb_sel;
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wire wb_we;
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wire wb_stb;
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wire wb_ack;
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wire [4*32-1:0] GPO;
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wire [4*32-1:0] GPI;
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assign o_GPO_A = GPO[32*1-1:32*0];
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assign o_GPO_B = GPO[32*2-1:32*1];
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assign o_GPO_C = GPO[32*3-1:32*2];
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assign o_GPO_D = GPO[32*4-1:32*3];
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assign GPI[32*1-1:32*0] = i_GPI_A;
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assign GPI[32*2-1:32*1] = i_GPI_B;
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assign GPI[32*3-1:32*2] = i_GPI_C;
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assign GPI[32*4-1:32*3] = i_GPI_D;
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serving #(
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.memfile(memfile),
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.memsize(memsize),
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.sim(sim),
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.RESET_STRATEGY("MINI"),
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.WITH_CSR(1)
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) serv (
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.i_clk(i_clk),
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.i_rst(i_rst),
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.i_timer_irq(1'b0),
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.i_wb_rdt(wb_rdt),
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.i_wb_ack(wb_ack),
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.o_wb_adr(wb_adr),
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.o_wb_dat(wb_dat),
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.o_wb_sel(wb_sel),
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.o_wb_we(wb_we),
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.o_wb_stb(wb_stb)
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);
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wb_gpio_banks #(
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.BASE_ADDR(32'h40000000),
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.NUM_BANKS(4)
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) gpio (
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.i_wb_clk(i_clk),
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.i_wb_rst(i_rst),
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.i_wb_dat(wb_dat),
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.i_wb_adr(wb_adr),
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.i_wb_we(wb_we),
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.i_wb_stb(wb_stb),
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.i_wb_sel(wb_sel),
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.i_gpio(GPI),
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.o_wb_rdt(wb_rdt),
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.o_wb_ack(wb_ack),
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.o_gpio(GPO)
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);
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endmodule |