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fpga_modem
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f2f96448303e0e53c4c705fe2746ee23f1d23bc3
fpga_modem
/
boards
/
mimas_v1
History
Joppe Blondel
8f4e887b9d
Added JTAG interface with testbench
2026-02-23 15:37:49 +01:00
..
ip
Added PLL/clock generator and SD RC model
2025-10-19 15:36:55 +02:00
constraints.ucf
Added JTAG interface with testbench
2026-02-23 15:37:49 +01:00
