Files
fpga_modem/cores/util/clog2/clog2.core

17 lines
298 B
Core

CAPI=2:
name: joppeb:util:clog2:1.0
description: Verilog-2001 compatible ceil(log2(x)) macro header
filesets:
include:
files:
- clog2.vh:
is_include_file: true
file_type: verilogSource
targets:
default:
filesets:
- include