66 lines
1.3 KiB
Verilog
66 lines
1.3 KiB
Verilog
`timescale 1ns/1ps
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module tb_serving();
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// Clock and reset generation
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reg clk;
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reg resetn;
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initial clk <= 1'b0;
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always #4.17 clk <= !clk;
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initial begin
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resetn <= 1'b1;
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#(4.17*40) resetn <= 1'b0;
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#(4.17*40) resetn <= 1'b1;
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end;
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// Default run
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initial begin
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$dumpfile("out.vcd");
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$dumpvars;
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#50_000
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$finish;
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end;
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wire [31:0] wb_adr;
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wire [31:0] wb_dat;
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wire [3:0] wb_sel;
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wire wb_we;
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wire wb_stb;
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wire [31:0] wb_rdt;
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wire wb_ack;
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wire [31:0] GPIO;
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serving #(
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.memfile("../sw/blinky/blinky.hex"),
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.memsize(8192),
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.sim(1'b1),
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.RESET_STRATEGY("MINI"),
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.WITH_CSR(1)
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) serv (
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.i_clk(clk),
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.i_rst(!resetn),
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.i_timer_irq(1'b0),
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.i_wb_rdt(wb_rdt),
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.i_wb_ack(wb_ack),
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.o_wb_adr(wb_adr),
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.o_wb_dat(wb_dat),
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.o_wb_sel(wb_sel),
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.o_wb_we(wb_we),
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.o_wb_stb(wb_stb)
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);
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wb_gpio #(
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.address(32'h40000000)
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) gpio (
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.i_wb_clk(clk),
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.i_wb_dat(wb_dat),
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.i_wb_adr(wb_adr),
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.i_wb_we(wb_we),
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.i_wb_stb(wb_stb),
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.i_wb_sel(wb_sel),
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.o_wb_rdt(wb_rdt),
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.o_wb_ack(wb_ack),
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.o_gpio(GPIO)
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);
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endmodule |