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fpga_modem
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8f4e887b9d44c2ffef319db32a417e26d4c24dee
fpga_modem
/
scripts
History
Joppe Blondel
8f4e887b9d
Added JTAG interface with testbench
2026-02-23 15:37:49 +01:00
..
filter_design
Added K IIR lpf filter
2025-10-19 17:02:29 +02:00
gen_sin_lut.py
Using remotesyn and added NCO
2025-10-05 23:20:25 +02:00
hex_to_coe.py
Working SERV cpu
2026-02-22 18:48:17 +01:00
hex_to_mif.py
Working SERV cpu
2026-02-22 18:48:17 +01:00
jtag_write_user_impact.py
Added JTAG interface with testbench
2026-02-23 15:37:49 +01:00
planahead.sh
Added soclet with gpio banks to top
2026-02-22 20:00:42 +01:00
planahead.tcl
Added soclet with gpio banks to top
2026-02-22 20:00:42 +01:00