23 lines
548 B
Verilog
23 lines
548 B
Verilog
`timescale 1ns/1ps
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// =============================================================================
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// Sigma-Delta sampler
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// Samples A>B at clk
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// =============================================================================
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module sigmadelta_sampler(
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input wire clk,
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input wire a,
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input wire b,
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output wire o
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);
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wire comp_out;
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lvds_comparator comp (
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.a(a), .b(b), .o(comp_out)
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);
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reg registered_comp_out;
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always @(posedge clk) registered_comp_out <= o;
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assign o = registered_comp_out;
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endmodule |