103 lines
2.2 KiB
Verilog
103 lines
2.2 KiB
Verilog
`timescale 1ns/1ps
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module toplevel #(
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parameter sim = 0
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)(
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input wire aclk,
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input wire aresetn,
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output wire led_green,
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output wire led_red,
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output wire[5:0] r2r,
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output wire[7:0] LED
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);
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`include "conv.vh"
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// Clocking
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wire clk_100;
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assign clk_100 = aclk;
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wire clk_15;
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clkgen #(
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.CLK_IN_HZ(100000000),
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.CLKFX_DIVIDE(20),
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.CLKFX_MULTIPLY(3)
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) clk_gen_15 (
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.clk_in(clk_100),
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.clk_out(clk_15)
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);
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// Reset conditioning for button input:
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// - asynchronous assert when button is pressed (aresetn=0)
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// - synchronous, debounced deassert in clk_15 domain
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localparam [17:0] RESET_RELEASE_CYCLES = sim ? 18'd16 : 18'd150000; // ~10 ms @ 15 MHz on hardware
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reg [17:0] rst_cnt = 18'd0;
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reg sys_reset_r = 1'b1;
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always @(posedge clk_15 or negedge aresetn) begin
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if (!aresetn) begin
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rst_cnt <= 18'd0;
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sys_reset_r <= 1'b1;
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end else if (sys_reset_r) begin
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if (rst_cnt == RESET_RELEASE_CYCLES - 1'b1)
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sys_reset_r <= 1'b0;
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else
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rst_cnt <= rst_cnt + 1'b1;
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end
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end
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wire sys_reset = sys_reset_r;
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wire sys_resetn = !sys_reset_r;
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wire [31:0] GPIO_A;
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wire [31:0] GPIO_B;
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wire [31:0] GPIO_C;
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wire [31:0] GPIO_D;
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wire test;
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mcu #(
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.memfile("../sw/sweep/sweep.hex"),
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.sim(sim),
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.jtag(1)
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) mcu (
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.i_clk(clk_15),
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.i_rst(sys_reset),
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.i_GPI_A(GPIO_A),
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.i_GPI_B(GPIO_B),
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.i_GPI_C(GPIO_C),
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.i_GPI_D(GPIO_D),
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.o_GPO_A(GPIO_A),
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.o_GPO_B(GPIO_B),
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.o_GPO_C(GPIO_C),
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.o_GPO_D(GPIO_D)
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);
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wire [15:0] sin_q15;
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wire clk_en;
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nco_q15 #(
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.CLK_HZ(15_000_000),
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.FS_HZ(80_000)
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) nco (
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.clk (clk_15),
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.rst_n (sys_resetn),
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.freq_hz(GPIO_A),
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.sin_q15(sin_q15),
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.cos_q15(),
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.clk_en (clk_en)
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);
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reg [5:0] dac_code;
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always @(posedge clk_15) begin
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dac_code <= q15_to_uq16(sin_q15) >> 10;
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end
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assign r2r = dac_code;
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assign LED = GPIO_B[7:0];
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assign led_green = GPIO_C[0];
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assign led_red = GPIO_C[1];
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endmodule
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