joppe/fpga_modem
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165faefa59d6dd69a246376efc083ae2e489f5bc
fpga_modem/rtl
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Joppe Blondel 165faefa59 Added decimation
2025-10-19 17:26:09 +02:00
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arch
Added PLL/clock generator and SD RC model
2025-10-19 15:36:55 +02:00
core
Added decimation
2025-10-19 17:26:09 +02:00
toplevel
Added PLL/clock generator and SD RC model
2025-10-19 15:36:55 +02:00
util
Added PLL/clock generator and SD RC model
2025-10-19 15:36:55 +02:00