43 lines
801 B
Verilog
43 lines
801 B
Verilog
`timescale 1ns/1ps
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module tb_nco_q15();
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// Clock and reset generation
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reg clk;
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reg resetn;
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initial clk <= 1'b0;
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initial resetn <= 1'b0;
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always #4.17 clk <= !clk;
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initial #40 resetn <= 1'b1;
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// Default run
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initial begin
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$dumpfile("out.vcd");
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$dumpvars;
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#5_000_000
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$finish;
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end;
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reg [31:0] freq;
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wire [15:0] sin_q15;
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wire [15:0] cos_q15;
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wire out_en;
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nco_q15 #(.CLK_HZ(120_000_000), .FS_HZ(40_000)) nco (
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.clk (clk),
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.rst_n (resetn),
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.freq_hz(freq),
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.sin_q15(sin_q15),
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.cos_q15(cos_q15),
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.clk_en (out_en)
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);
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initial begin
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freq = 32'h0;
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#100
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freq = 32'd1000;
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#2_500_000
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freq = 32'd2000;
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end;
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endmodule |