Files
fpga_modem/scripts/planahead.tcl
2025-10-05 23:20:25 +02:00

6 lines
446 B
Tcl

create_project project_1 /tmp/project_1 -part xc6slx9tqg144-2
set_property design_mode GateLvl [current_fileset]
add_files -norecurse /data/joppe/projects/modem/out/synth/synth.ngc
import_files -force -norecurse
import_files -fileset constrs_1 -force -norecurse /data/joppe/projects/modem/boards/mimas_v1/constraints.ucf
import_as_run -run impl_1 -twx /data/joppe/projects/modem/out/synth/timing.twx /data/joppe/projects/modem/out/synth/synth.ncd