Joppe Blondel
838204653a
TODO: think of other way of shifting in data. Bit errors make uploading difficult
46 lines
882 B
Verilog
46 lines
882 B
Verilog
`timescale 1ns/1ps
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module tb_top_generic();
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reg aclk;
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reg aresetn;
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wire led_green;
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wire led_red;
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wire [5:0] r2r;
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wire [7:0] LED;
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// 100 MHz board input clock
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initial aclk = 1'b0;
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always #33.33 aclk = ~aclk;
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// Hold reset low, then release
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initial begin
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aresetn = 1'b0;
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#200;
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aresetn = 1'b1;
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end
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top_generic #(
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.sim(1)
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) dut (
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.aclk(aclk),
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.aresetn(aresetn),
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.led_green(led_green),
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.led_red(led_red),
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.r2r(r2r),
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.LED(LED)
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);
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// Ensure firmware path resolves from repository root when simulating.
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defparam dut.mcu.memfile = "sw/sweep/sweep.hex";
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initial begin
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$dumpfile("out.vcd");
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$dumpvars(0, tb_top_generic);
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// Let firmware run for a while.
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#2_000_000;
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$finish;
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end
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endmodule
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