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Added everything from the other system

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This commit is contained in:
Joppe Blondel
2026-02-28 21:46:59 +01:00
parent 907f244b24
commit efd366c067
34 changed files with 1601 additions and 57 deletions
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110
cores/system/test/rtl/toplevel.v
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@@ -1,6 +1,8 @@
`timescale 1ns/1ps
module toplevel(
module toplevel #(
parameter sim = 0
)(
input wire aclk,
input wire aresetn,
@@ -11,6 +13,7 @@ module toplevel(
output wire[7:0] LED
);
`include "conv.vh"
// Clocking
wire clk_100;
@@ -25,56 +28,75 @@ module toplevel(
.clk_out(clk_15)
);
wire wb_rst;
assign wb_rst = ~aresetn;
wire [31:0] wb_adr;
wire [31:0] wb_dat_w;
wire [31:0] wb_dat_r;
wire [3:0] wb_sel;
wire wb_we;
wire wb_cyc;
wire wb_stb;
wire wb_ack;
wire wb_cmd_reset;
// Reset conditioning for button input:
// - asynchronous assert when button is pressed (aresetn=0)
// - synchronous, debounced deassert in clk_15 domain
localparam [17:0] RESET_RELEASE_CYCLES = sim ? 18'd16 : 18'd150000; // ~10 ms @ 15 MHz on hardware
reg [17:0] rst_cnt = 18'd0;
reg sys_reset_r = 1'b1;
always @(posedge clk_15 or negedge aresetn) begin
if (!aresetn) begin
rst_cnt <= 18'd0;
sys_reset_r <= 1'b1;
end else if (sys_reset_r) begin
if (rst_cnt == RESET_RELEASE_CYCLES - 1'b1)
sys_reset_r <= 1'b0;
else
rst_cnt <= rst_cnt + 1'b1;
end
end
wire sys_reset = sys_reset_r;
wire sys_resetn = !sys_reset_r;
wire [31:0] gpio_out;
wire gpio_rst;
assign gpio_rst = wb_rst;
wire [31:0] GPIO_A;
wire [31:0] GPIO_B;
wire [31:0] GPIO_C;
wire [31:0] GPIO_D;
jtag_wb_bridge u_jtag_wb_bridge (
wire test;
mcu #(
.memfile("../sw/sweep/sweep.hex"),
.sim(sim),
.jtag(1)
) mcu (
.i_clk(clk_15),
.i_rst(wb_rst),
.o_wb_adr(wb_adr),
.o_wb_dat(wb_dat_w),
.o_wb_sel(wb_sel),
.o_wb_we(wb_we),
.o_wb_cyc(wb_cyc),
.o_wb_stb(wb_stb),
.i_wb_rdt(wb_dat_r),
.i_wb_ack(wb_ack),
.o_cmd_reset(wb_cmd_reset)
.i_rst(sys_reset),
.i_GPI_A(GPIO_A),
.i_GPI_B(GPIO_B),
.i_GPI_C(GPIO_C),
.i_GPI_D(GPIO_D),
.o_GPO_A(GPIO_A),
.o_GPO_B(GPIO_B),
.o_GPO_C(GPIO_C),
.o_GPO_D(GPIO_D)
);
wb_gpio #(
.address(32'h00000000)
) u_wb_gpio (
.i_wb_clk(clk_15),
.i_wb_rst(gpio_rst),
.i_wb_adr(wb_adr),
.i_wb_dat(wb_dat_w),
.i_wb_sel(wb_sel),
.i_wb_we(wb_we),
.i_wb_stb(wb_cyc & wb_stb),
.i_gpio(gpio_out),
.o_wb_rdt(wb_dat_r),
.o_wb_ack(wb_ack),
.o_gpio(gpio_out)
wire [15:0] sin_q15;
wire clk_en;
nco_q15 #(
.CLK_HZ(15_000_000),
.FS_HZ(80_000)
) nco (
.clk (clk_15),
.rst_n (sys_resetn),
.freq_hz(GPIO_A),
.sin_q15(sin_q15),
.cos_q15(),
.clk_en (clk_en)
);
assign led_green = aresetn;
assign led_red = wb_cmd_reset;
assign LED = gpio_out[7:0];
assign r2r = gpio_out[13:8];
reg [5:0] dac_code;
always @(posedge clk_15) begin
dac_code <= q15_to_uq16(sin_q15) >> 10;
end
assign r2r = dac_code;
assign LED = GPIO_B[7:0];
assign led_green = GPIO_C[0];
assign led_red = GPIO_C[1];
endmodule

8
cores/system/test/sw/.gitignore vendored Normal file
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@@ -0,0 +1,8 @@
*.o
*.hex
*.bin
*.map
*.elf.asm
*.elf
*.coe
*.mif

47
cores/system/test/sw/sweep/Makefile Normal file
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@@ -0,0 +1,47 @@
TOOLCHAIN_PREFIX ?= riscv64-elf-
CC := $(TOOLCHAIN_PREFIX)gcc
OBJCOPY := $(TOOLCHAIN_PREFIX)objcopy
OBJDUMP := $(TOOLCHAIN_PREFIX)objdump
SIZE := $(TOOLCHAIN_PREFIX)size
TARGET := sweep
SRCS_C := sweep.c
SRCS_S := start.s
OBJS := $(SRCS_C:.c=.o) $(SRCS_S:.s=.o)
ARCH_FLAGS := -march=rv32i_zicsr -mabi=ilp32
CFLAGS := $(ARCH_FLAGS) -Os -ffreestanding -fno-builtin -Wall -Wextra
ASFLAGS := $(ARCH_FLAGS)
LDFLAGS := $(ARCH_FLAGS) -nostdlib -nostartfiles -Wl,-Bstatic,-Tlink.ld,--gc-sections,-Map,$(TARGET).map
.PHONY: all clean disasm size
all: $(TARGET).elf $(TARGET).bin $(TARGET).hex $(TARGET).elf.asm
$(TARGET).elf: $(OBJS) link.ld
$(CC) $(LDFLAGS) -o $@ $(OBJS)
%.o: %.c
$(CC) $(CFLAGS) -c -o $@ $<
%.o: %.s
$(CC) $(ASFLAGS) -c -o $@ $<
$(TARGET).bin: $(TARGET).elf
$(OBJCOPY) -O binary $< $@
$(TARGET).hex: $(TARGET).bin
hexdump -v -e '1/4 "%08x\n"' $< > $@
$(TARGET).elf.asm: $(TARGET).elf
$(OBJDUMP) -d -S $< > $@
disasm: $(TARGET).elf.asm
size: $(TARGET).elf
$(SIZE) $<
clean:
rm -f $(TARGET).elf $(TARGET).bin $(TARGET).hex $(TARGET).coe $(TARGET).mif \
$(TARGET).elf.asm $(TARGET).map $(OBJS)

35
cores/system/test/sw/sweep/link.ld Normal file
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@@ -0,0 +1,35 @@
OUTPUT_ARCH("riscv")
ENTRY(_start)
MEMORY
{
RAM (rwx) : ORIGIN = 0x00000000, LENGTH = 8192
}
SECTIONS
{
.text :
{
KEEP(*(.text.init))
*(.text .text.*)
*(.rodata .rodata.*)
} > RAM
.data :
{
*(.data .data.*)
} > RAM
.bss (NOLOAD) :
{
__bss_start = .;
*(.bss .bss.*)
*(.sbss .sbss.*)
*(.scommon)
*(COMMON)
__bss_end = .;
} > RAM
. = ALIGN(4);
__stack_top = ORIGIN(RAM) + LENGTH(RAM);
}

99
cores/system/test/sw/sweep/start.s Normal file
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@@ -0,0 +1,99 @@
.section .text.init
.globl _start
.type _start, @function
_start:
la sp, __stack_top
# Zero .bss
la t0, __bss_start
la t1, __bss_end
1:
bgeu t0, t1, 2f
sw zero, 0(t0)
addi t0, t0, 4
j 1b
2:
call main
3:
j 3b
.size _start, .-_start
.section .text
.globl trap_entry
.type trap_entry, @function
trap_entry:
# Save full integer context (except x0/x2) because an interrupt can
# preempt code with live values in any register, not just caller-saved.
addi sp, sp, -128
sw ra, 124(sp)
sw gp, 120(sp)
sw tp, 116(sp)
sw t0, 112(sp)
sw t1, 108(sp)
sw t2, 104(sp)
sw s0, 100(sp)
sw s1, 96(sp)
sw a0, 92(sp)
sw a1, 88(sp)
sw a2, 84(sp)
sw a3, 80(sp)
sw a4, 76(sp)
sw a5, 72(sp)
sw a6, 68(sp)
sw a7, 64(sp)
sw s2, 60(sp)
sw s3, 56(sp)
sw s4, 52(sp)
sw s5, 48(sp)
sw s6, 44(sp)
sw s7, 40(sp)
sw s8, 36(sp)
sw s9, 32(sp)
sw s10, 28(sp)
sw s11, 24(sp)
sw t3, 20(sp)
sw t4, 16(sp)
sw t5, 12(sp)
sw t6, 8(sp)
csrr t0, mcause
li t1, 0x80000007 # machine timer interrupt (RV32)
bne t0, t1, 1f
call timer_isr # C function that ACKs/clears the timer so i_timer_irq goes low
1:
lw t6, 8(sp)
lw t5, 12(sp)
lw t4, 16(sp)
lw t3, 20(sp)
lw s11, 24(sp)
lw s10, 28(sp)
lw s9, 32(sp)
lw s8, 36(sp)
lw s7, 40(sp)
lw s6, 44(sp)
lw s5, 48(sp)
lw s4, 52(sp)
lw s3, 56(sp)
lw s2, 60(sp)
lw a7, 64(sp)
lw a6, 68(sp)
lw a5, 72(sp)
lw a4, 76(sp)
lw a3, 80(sp)
lw a2, 84(sp)
lw a1, 88(sp)
lw a0, 92(sp)
lw s1, 96(sp)
lw s0, 100(sp)
lw t2, 104(sp)
lw t1, 108(sp)
lw t0, 112(sp)
lw tp, 116(sp)
lw gp, 120(sp)
lw ra, 124(sp)
addi sp, sp, 128
mret

45
cores/system/test/sw/sweep/sweep.c Normal file
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@@ -0,0 +1,45 @@
#include <stdint.h>
#define GPIO_BASE 0x40000000u
static volatile uint32_t * const R_FREQ = (volatile uint32_t *)(GPIO_BASE+0);
static volatile uint32_t * const LEDS = (volatile uint32_t *)(GPIO_BASE+4);
static volatile uint32_t * const LEDGR = (volatile uint32_t *)(GPIO_BASE+8);
#define TIMER_BASE 0x40010000u
static volatile uint32_t * const TIMER = (volatile uint32_t *)(TIMER_BASE+0);
#define MSTATUS_MIE (1u << 3)
#define MIE_MTIE (1u << 7)
extern void trap_entry();
static inline void irq_init() {
/* mtvec first */
asm volatile ("csrw mtvec, %0" :: "r"(trap_entry));
/* enable machine timer interrupt */
asm volatile ("csrs mie, %0" :: "r"(MIE_MTIE));
/* global enable last */
asm volatile ("csrs mstatus, %0" :: "r"(MSTATUS_MIE));
}
void timer_isr(){
static int set = 0;
*TIMER = 1840000*8;
*LEDGR = ~(*LEDGR);
}
void main(){
irq_init();
*LEDGR = 3;
*TIMER = 1840000*2;
for(;;){
for(int i=1000; i<10000; i++){
*R_FREQ = i;
for(int j=0; j<80; j++) asm volatile("nop");
}
}
}

11
cores/system/test/test.core
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@@ -7,12 +7,18 @@ filesets:
rtl:
depend:
- joppeb:primitive:clkgen
- joppeb:wb:jtag_wb_bridge
- joppeb:wb:wb_gpio
- joppeb:system:mcu
- joppeb:signal:nco_q15
- joppeb:util:conv
files:
- rtl/toplevel.v
file_type: verilogSource
sw:
files:
- sw/sweep/sweep.hex
file_type: user
mimas:
files:
- mimas.ucf : {file_type : UCF}
@@ -28,6 +34,7 @@ targets:
filesets:
- rtl
- mimas
- sw
toplevel: toplevel
parameters:
- FPGA_SPARTAN6=true