control register instead of reset output

cores/signal/signal_scope/tool/capture_plot.py

@@ -6,6 +6,11 @@ from pathlib import Path
 
 import matplotlib.pyplot as plt
 
+MEM_BASE = 0x00000000
+REG_BASE = 0x80000000
+REG_CONTROL = REG_BASE + 0x00
+REG_STATUS = REG_BASE + 0x04
+
 
 def _add_bridge_module_path() -> None:
     here = Path(__file__).resolve()
@@ -64,16 +69,15 @@ def parse_args() -> argparse.Namespace:
 def capture_once(bridge, args: argparse.Namespace) -> list[tuple[int, int, int, int]]:
     samples = []
     frame_count = args.depth
-    print("[signal_scope] Arming scope (set_reset=1 -> 0)...")
-    bridge.set_reset(True)
-    bridge.set_reset(False)
+    print("[signal_scope] Arming scope (write REG_CONTROL bit0=1)...")
+    bridge.write32(REG_CONTROL, 0x1)
     if args.wait_s > 0:
         print(f"[signal_scope] Waiting {args.wait_s:.3f}s for capture to complete...")
         time.sleep(args.wait_s)
 
     print(f"[signal_scope] Reading back {frame_count} frames...")
     for idx in range(frame_count):
-        base = idx * 8
+        base = MEM_BASE + idx * 8
         low = bridge.read32(base)
         high = bridge.read32(base + 4)
 
@@ -151,6 +155,8 @@ def main() -> int:
         bridge.clear_flags()
         bridge.ping()
         print("[signal_scope] Bridge ready")
+        status = bridge.read32(REG_STATUS)
+        print(f"[signal_scope] Status: 0x{status:08x}")
 
         fig, ax = plt.subplots(figsize=(12, 4))
         capture_idx = 1