Test with modem connected

2026-03-05 19:49:44 +01:00
parent 08c0f6967b
commit e0769f0c0d
7 changed files with 8300 additions and 11 deletions
--- a/cores/system/mimas_sd_adc_r2r/rtl/toplevel.v
+++ b/cores/system/mimas_sd_adc_r2r/rtl/toplevel.v
@@ -60,7 +60,7 @@ module toplevel(
    // signal_q15 is unipolar and biased (0-3.3V -> 0..32767)
    reg signed [15:0] signal_unbiased_q15 = 16'sd0;
    reg signal_unbiased_valid = 1'b0;
-    localparam bias = 12050;
+    localparam bias = 2**14;
    localparam gain = 2;
    always @(posedge clk_15) begin
        if (sys_reset_r) begin
@@ -91,7 +91,7 @@ module toplevel(


    signal_scope_q15 #(
-        .depth(2**10),
+        .depth(2**13),
        .chain(1)
    ) scope1 (
        .i_clk(clk_15),