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Test with modem connected

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This commit is contained in:
Joppe Blondel
2026-03-05 19:49:44 +01:00
parent 08c0f6967b
commit e0769f0c0d
7 changed files with 8300 additions and 11 deletions
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6
cores/signal/sd_adc_q15/rtl/sd_adc_q15.v
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@@ -38,7 +38,7 @@ module sd_adc_q15 #(
);
lpf_iir_q15_k #(
.K(6)
.K(8)
) lpf (
.i_clk(i_clk_15), .i_rst_n(i_rst_n),
.i_x_q15(raw_sample_q15),
@@ -46,8 +46,8 @@ module sd_adc_q15 #(
);
decimate_by_r_q15 #(
.R(200), // 15MHz/200 = 75KHz
// .R(375), // 15MHz/375 = 40KHz
// .R(200), // 15MHz/200 = 75KHz
.R(375), // 15MHz/375 = 40KHz
.CNT_W(10)
) decimate (
.i_clk(i_clk_15), .i_rst_n(i_rst_n),

29
cores/signal/signal_scope/rtl/signal_scope_q15.v
View File

@@ -57,6 +57,10 @@ module signal_scope_q15 #(
wire [3:0] wb_reg_idx = wb_adr[5:2];
reg [15:0] trigger_sample;
reg trigger_sample_valid;
reg wb_mem_read_pending;
reg wb_mem_read_half;
reg wb_mem_read_oob;
reg [16*4-1:0] wb_mem_rdata;
jtag_wb_bridge #(
.chain(chain),
@@ -119,6 +123,10 @@ module signal_scope_q15 #(
signal_b_pending <= 1'b0;
signal_c_pending <= 1'b0;
signal_d_pending <= 1'b0;
wb_mem_read_pending <= 1'b0;
wb_mem_read_half <= 1'b0;
wb_mem_read_oob <= 1'b0;
wb_mem_rdata <= {(16*4){1'b0}};
end else begin
// Sample signals
@@ -188,9 +196,16 @@ module signal_scope_q15 #(
// WB slave response: register window + capture memory window.
arm_req <= 1'b0;
wb_ack <= wb_cyc & wb_stb & !wb_ack;
if(wb_cyc & wb_stb & !wb_ack) begin
wb_ack <= 1'b0;
if(wb_mem_read_pending) begin
wb_ack <= 1'b1;
wb_rdt <= wb_mem_read_oob ? 32'b0 :
(wb_mem_read_half ? wb_mem_rdata[63:32] : wb_mem_rdata[31:0]);
wb_mem_read_pending <= 1'b0;
end else if(wb_cyc & wb_stb) begin
if(wb_we) begin
wb_ack <= 1'b1;
wb_rdt <= 32'b0;
if(wb_is_reg) begin
// Keep register write decode in one case so new writable registers
@@ -217,6 +232,7 @@ module signal_scope_q15 #(
end
end else begin
if(wb_is_reg) begin
wb_ack <= 1'b1;
case(wb_reg_idx)
// [3:2]=trigger_channel, [1]=trigger_enable, [0]=arm(write pulse only/read 0).
reg_control: wb_rdt <= {28'b0, trigger_channel, trigger_enable, 1'b0};
@@ -225,11 +241,12 @@ module signal_scope_q15 #(
reg_trig_val: wb_rdt <= {16'b0, trig_val};
default: wb_rdt <= 32'b0;
endcase
end else if(wb_mem_idx <= depth_last) begin
// A single frame is 64-bit: {a, b, c, d}. WB reads low/high 32-bit halves.
wb_rdt <= wb_adr[2] ? mem[wb_mem_idx][63:32] : mem[wb_mem_idx][31:0];
end else begin
wb_rdt <= 32'b0;
// Synchronous RAM read for BRAM inference: issue read now, acknowledge next cycle.
wb_mem_rdata <= mem[wb_mem_idx];
wb_mem_read_half <= wb_adr[2];
wb_mem_read_oob <= (wb_mem_idx > depth_last);
wb_mem_read_pending <= 1'b1;
end
end
end