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Added trigger to scope

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This commit is contained in:
Joppe Blondel
2026-03-05 16:13:26 +01:00
parent e0a276cd18
commit cfdec1aec7
2 changed files with 96 additions and 18 deletions
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65
cores/signal/signal_scope/rtl/signal_scope_q15.v
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@@ -20,11 +20,19 @@ module signal_scope_q15 #(
localparam [31:0] reg_base_addr = 32'h8000_0000;
localparam [3:0] reg_control = 4'h0;
localparam [3:0] reg_status = 4'h1;
localparam [3:0] reg_trig_val = 4'h2;
(* ram_style = "block" *) reg [16*4-1:0] mem[depth-1:0];
reg [aw-1:0] counter;
reg count_enable;
reg arm_req;
reg trigger_enable;
reg scope_armed;
reg scope_triggered;
reg capture_done;
reg [15:0] trig_val;
reg [15:0] signal_a_prev;
reg signal_a_prev_valid;
reg [15:0] signal_a;
reg [15:0] signal_b;
@@ -69,8 +77,15 @@ module signal_scope_q15 #(
counter <= {aw{1'b0}};
count_enable <= 1'b0;
arm_req <= 1'b0;
trigger_enable <= 1'b0;
scope_armed <= 1'b0;
scope_triggered <= 1'b0;
capture_done <= 1'b0;
wb_ack <= 1'b0;
wb_rdt <= 32'b0;
trig_val <= 16'h0000;
signal_a_prev <= 16'h0000;
signal_a_prev_valid <= 1'b0;
signal_a <= 0;
signal_b <= 0;
signal_c <= 0;
@@ -85,6 +100,18 @@ module signal_scope_q15 #(
if(i_signal_valid_a) begin
signal_a <= i_signal_a;
signal_a_pending <= 1'b1;
// Trigger on signal_a rising across trig_val.
if(scope_armed && trigger_enable && !count_enable) begin
if(signal_a_prev_valid &&
($signed(signal_a_prev) < $signed(trig_val)) &&
($signed(i_signal_a) >= $signed(trig_val))) begin
count_enable <= 1'b1;
scope_triggered <= 1'b1;
end
signal_a_prev <= i_signal_a;
signal_a_prev_valid <= 1'b1;
end
end
if(i_signal_valid_b) begin
signal_b <= i_signal_b;
@@ -99,10 +126,14 @@ module signal_scope_q15 #(
signal_d_pending <= 1'b1;
end
// Arm/rearm capture on control-register command pulse.
// Arm/rearm capture. If trigger is disabled, start capture immediately.
if(arm_req) begin
counter <= {aw{1'b0}};
count_enable <= 1'b1;
count_enable <= !trigger_enable;
scope_armed <= 1'b1;
scope_triggered <= !trigger_enable;
capture_done <= 1'b0;
signal_a_prev_valid <= 1'b0;
signal_a_pending <= 1'b0;
signal_b_pending <= 1'b0;
signal_c_pending <= 1'b0;
@@ -114,10 +145,15 @@ module signal_scope_q15 #(
if(counter <= depth_last) begin
mem[counter] <= {signal_a, signal_b, signal_c, signal_d};
counter <= counter + {{(aw-1){1'b0}}, 1'b1};
if(counter == depth_last)
if(counter == depth_last) begin
count_enable <= 1'b0;
scope_armed <= 1'b0;
capture_done <= 1'b1;
end
end else begin
count_enable <= 1'b0;
scope_armed <= 1'b0;
capture_done <= 1'b1;
end
signal_a_pending <= 1'b0;
signal_b_pending <= 1'b0;
@@ -136,9 +172,17 @@ module signal_scope_q15 #(
// can be added without touching memory-path logic.
case(wb_reg_idx)
reg_control: begin
// Bit 0: write-1 to arm/rearm scope (pulse).
if(wb_sel[0] && wb_dat[0])
arm_req <= 1'b1;
if(wb_sel[0]) begin
// Bit 0: write-1 pulse to arm/rearm scope.
if(wb_dat[0])
arm_req <= 1'b1;
// Bit 1: trigger enable.
trigger_enable <= wb_dat[1];
end
end
reg_trig_val: begin
if(wb_sel[0]) trig_val[7:0] <= wb_dat[7:0];
if(wb_sel[1]) trig_val[15:8] <= wb_dat[15:8];
end
default: begin
end
@@ -147,10 +191,11 @@ module signal_scope_q15 #(
end else begin
if(wb_is_reg) begin
case(wb_reg_idx)
// Write-pulse register: reads as zero.
reg_control: wb_rdt <= 32'b0;
// Basic status for polling/debug.
reg_status: wb_rdt <= {30'b0, count_enable, (counter == depth_last)};
// [1]=trigger_enable, [0]=arm bit is write-pulse only.
reg_control: wb_rdt <= {30'b0, trigger_enable, 1'b0};
// [0]=triggered, [1]=capturing, [2]=armed, [3]=done
reg_status: wb_rdt <= {28'b0, capture_done, scope_armed, count_enable, scope_triggered};
reg_trig_val: wb_rdt <= {16'b0, trig_val};
default: wb_rdt <= 32'b0;
endcase
end else if(wb_mem_idx <= depth_last) begin