Signal scope

cores/system/mimas_sd_adc_r2r/mimas_sd_adc_r2r.core

@@ -9,6 +9,7 @@ filesets:
             - joppeb:primitive:clkgen
             - joppeb:signal:sd_adc_q15
             - joppeb:util:conv
+            - joppeb:signal:signal_scope_q15
         files:
             - rtl/toplevel.v
         file_type: verilogSource

cores/system/mimas_sd_adc_r2r/rtl/toplevel.v

@@ -60,7 +60,7 @@ module toplevel(
     // signal_q15 is unipolar and biased (0-3.3V -> 0..32767)
     reg signed [15:0] signal_unbiased_q15 = 16'sd0;
     reg signal_unbiased_valid = 1'b0;
-    localparam bias = 2**14;
+    localparam bias = 12050;
     localparam gain = 2;
     always @(posedge clk_15) begin
         if (sys_reset_r) begin
@@ -88,4 +88,19 @@ module toplevel(
     assign LED[0] = signal_valid;
     assign LED[6:1] = dac_code;
     assign LED[7] = sys_reset_r;
+
+
+    signal_scope_q15 #(
+        .depth(2**10),
+        .chain(1)
+    ) scope1 (
+        .i_clk(clk_15),
+        .i_rst(sys_reset_r),
+        .i_signal_a(signal_q15),
+        .i_signal_valid_a(signal_valid),
+        .i_signal_b(signal_unbiased_q15),
+        .i_signal_valid_b(signal_unbiased_valid),
+        .i_signal_valid_c(signal_valid),
+        .i_signal_valid_d(signal_valid)
+    );
 endmodule