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Added JTAG interface with testbench

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This commit is contained in:
Joppe Blondel
2026-02-23 15:37:49 +01:00
parent 20cfece6e3
commit 8f4e887b9d
12 changed files with 731 additions and 24 deletions
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43
project.cfg
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@@ -4,6 +4,15 @@ version = 0.1
out_dir = out
build_dir = build
[target.ip]
toolchain = ISE_IP
ise_settings = /opt/Xilinx/14.7/ISE_DS/settings64.sh
family = spartan6
device = xc6slx9
package = tqg144
speedgrade = -2
files_def = boards/mimas_v1/ip/clk_gen.xco
[target.synth]
toolchain = ISE
ise_settings = /opt/Xilinx/14.7/ISE_DS/settings64.sh
@@ -56,31 +65,25 @@ files_other = rtl/util/rc_alpha_q15.vh
rtl/util/clog2.vh
sw/blinky/blinky.hex
[target.ip]
toolchain = ISE_IP
[target.jtag]
toolchain = ISE
ise_settings = /opt/Xilinx/14.7/ISE_DS/settings64.sh
family = spartan6
device = xc6slx9
package = tqg144
speedgrade = -2
files_def = boards/mimas_v1/ip/clk_gen.xco
toplevel = top_jtag
xst_opts = -vlgincdir rtl/util
files_other =
files_con = boards/mimas_v1/constraints.ucf
files_verilog = rtl/arch/spartan-6/jtag_if.v
rtl/arch/spartan-6/clk_gen.v
rtl/toplevel/top_jtag.v
[target.sim]
[target.svftest]
toolchain = iverilog
runtime = all
toplevel = tb_sigmadelta
ivl_opts = -Irtl/util
files_verilog = sim/tb/tb_nco_q15.v
sim/tb/tb_sigmadelta.v
sim/tb/tb_mul_const.v
rtl/core/nco_q15.v
rtl/core/lvds_comparator.v
rtl/core/sigmadelta_rcmodel_q15.v
rtl/core/sigmadelta_input_q15.v
rtl/core/mul_const.v
rtl/core/lpf_iir_q15_k.v
rtl/core/decimate_by_r_q15.v
sim/overrides/sigmadelta_sampler.v
sim/overrides/clk_gen.v
files_other = rtl/util/conv.vh
rtl/util/rc_alpha_q15.vh
toplevel = tb_svf
files_verilog = sim/tb/tb_svf.v
sim/overrides/jtag_if.v
files_other = sim/other/test.svf