Added decimation

project.cfg

@@ -24,6 +24,7 @@ files_verilog       = rtl/toplevel/top_generic.v
                       rtl/core/sigmadelta_rcmodel_q15.v
                       rtl/core/mul_const.v
                       rtl/core/lpf_iir_q15_k.v
+                      rtl/core/decimate_by_r_q15.v
                       rtl/arch/spartan-6/lvds_comparator.v
                       rtl/arch/spartan-6/clk_gen.v
 files_con           = boards/mimas_v1/constraints.ucf
@@ -52,6 +53,7 @@ files_verilog       = sim/tb/tb_nco_q15.v
                       rtl/core/sigmadelta_rcmodel_q15.v
                       rtl/core/mul_const.v
                       rtl/core/lpf_iir_q15_k.v
+                      rtl/core/decimate_by_r_q15.v
                       sim/overrides/sigmadelta_sampler.v
                       sim/overrides/clk_gen.v
 files_other         = rtl/util/conv.vh