Using remotesyn and added NCO
This commit is contained in:
21
scripts/gen_sin_lut.py
Normal file
21
scripts/gen_sin_lut.py
Normal file
@@ -0,0 +1,21 @@
|
||||
import math
|
||||
|
||||
# for i in range(0, 64, 4):
|
||||
# for j in range(4):
|
||||
# val = math.sin((i+j) * math.pi/256)
|
||||
# val = int(val*256*1.4)
|
||||
# print(f"6'd{i+j}: dout=8'd{val}; ", end='')
|
||||
# print('')
|
||||
|
||||
|
||||
N = 64 # quarter-wave samples
|
||||
AMP = 255 # 8-bit max
|
||||
for i in range(0, N, 4):
|
||||
line = []
|
||||
for j in range(4):
|
||||
k = i + j
|
||||
theta = k * math.pi / (2*N) # 0 .. (π/2)*(N-1)/N ; never hits 1.0
|
||||
val = int(math.floor(AMP * math.sin(theta) + 0.5)) # rounded, stays <=254
|
||||
if val > 255: val = 255
|
||||
line.append(f"6'd{k}: dout = 8'd{val};")
|
||||
print(' '.join(line))
|
||||
6
scripts/planahead.tcl
Normal file
6
scripts/planahead.tcl
Normal file
@@ -0,0 +1,6 @@
|
||||
create_project project_1 /tmp/project_1 -part xc6slx9tqg144-2
|
||||
set_property design_mode GateLvl [current_fileset]
|
||||
add_files -norecurse /data/joppe/projects/modem/out/synth/synth.ngc
|
||||
import_files -force -norecurse
|
||||
import_files -fileset constrs_1 -force -norecurse /data/joppe/projects/modem/boards/mimas_v1/constraints.ucf
|
||||
import_as_run -run impl_1 -twx /data/joppe/projects/modem/out/synth/timing.twx /data/joppe/projects/modem/out/synth/synth.ncd
|
||||
@@ -1 +0,0 @@
|
||||
openFPGALoader impl/pnr/modem.fs
|
||||
@@ -1 +0,0 @@
|
||||
gowin_sh scripts/run_all.tcl
|
||||
@@ -1,2 +0,0 @@
|
||||
open_project modem.gprj
|
||||
run all
|
||||
@@ -1,13 +0,0 @@
|
||||
cvc \
|
||||
+define+TIMING_SIM \
|
||||
+acc \
|
||||
+sdf_noerrors +sdf_nowarns \
|
||||
+show_canceled_e +suppress_warns+653+3102 \
|
||||
-v SIM/prim_tsim.v \
|
||||
impl/pnr/modem.vo \
|
||||
SIM/toplevel_tb.v \
|
||||
SIM/globals.v \
|
||||
+sdf_annotate+impl/pnr/modem.sdf+toplevel_tb.m_toplevel \
|
||||
+maxdelays \
|
||||
+librescan
|
||||
./cvcsim
|
||||
@@ -1,23 +0,0 @@
|
||||
# iverilog -o toplevel_tb.vp \
|
||||
# /opt/packages/gowin/IDE/simlib/gw1n/prim_sim.v \
|
||||
# HW/toplevel.v \
|
||||
# SIM/toplevel_tb.v
|
||||
# vvp toplevel_tb.vp
|
||||
|
||||
cvc +acc \
|
||||
+show_canceled_e +suppress_warns+653+3102 \
|
||||
+define+FAST_PLL_SIM \
|
||||
-v SIM/prim_tsim.v \
|
||||
\
|
||||
IP/gw_pllvr/gw_pllvr.v \
|
||||
IP/gw_clkdiv8/gw_clkdiv8.v \
|
||||
HW/toplevel.v \
|
||||
HW/sampling.v \
|
||||
\
|
||||
SIM/sigmadelta_sampler.v \
|
||||
\
|
||||
SIM/sampling_tb.v \
|
||||
SIM/globals.v \
|
||||
+librescan
|
||||
./cvcsim
|
||||
# SIM/toplevel_tb.v \
|
||||
Reference in New Issue
Block a user