joppe/fpga_modem
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Added wb formal script and added other sby tasks

Browse Source
This commit is contained in:
Joppe Blondel
2026-03-01 13:52:41 +01:00
parent cf483decad
commit 8289b0d090
6 changed files with 181 additions and 11 deletions
Download Patch File Download Diff File Expand all files Collapse all files

27
cores/wb/formal_checker/formal/formal_wb_master_checker.v
View File

@@ -68,6 +68,33 @@ module formal_wb_master_checker (
// R4: Once CYC is low, STB must also be low
if(!i_wb_cyc)
assert(!i_wb_stb);
// C0: We eventually initiate a request
cover(f_past_valid && !i_rst && !i_wb_rst && i_wb_cyc && i_wb_stb);
// C1: We eventually get an ACK during an active request
cover(f_past_valid && !i_rst && !i_wb_rst && i_wb_cyc && i_wb_stb && o_wb_ack);
// C2: ACK in the *same* cycle as the request (allowed by your A1)
cover(f_past_valid && !i_rst && !i_wb_rst && (i_wb_cyc && i_wb_stb) && o_wb_ack);
// C3: ACK one cycle *after* the request (also allowed by your A1)
// cover(f_past_valid && !i_rst && !i_wb_rst &&
// $past(i_wb_cyc && i_wb_stb) && o_wb_ack && !(i_wb_cyc && i_wb_stb));
// C4: A “wait state” happens: request asserted, no ACK for at least 1 cycle
cover(f_past_valid && !i_rst && !i_wb_rst &&
$past(i_wb_cyc && i_wb_stb && !o_wb_ack) &&
(i_wb_cyc && i_wb_stb && !o_wb_ack));
// C5: Read and write both occur (even if only once each)
cover(f_past_valid && !i_rst && !i_wb_rst && i_wb_cyc && i_wb_stb && !i_wb_we);
cover(f_past_valid && !i_rst && !i_wb_rst && i_wb_cyc && i_wb_stb && i_wb_we);
// C6: A transfer completes and the master drops CYC sometime after
cover(f_past_valid && !i_rst && !i_wb_rst &&
$past(i_wb_cyc && i_wb_stb && o_wb_ack) && !i_wb_cyc);
end
wire unused = &{1'b0, o_wb_rdt};

24
cores/wb/formal_checker/formal/formal_wb_slave_checker.v
View File

@@ -62,6 +62,30 @@ module formal_wb_slave_checker (
!i_wb_stb
)
assert(!o_wb_ack);
// C0: A request occurs at all
cover(f_past_valid && !i_rst && !i_wb_rst && i_wb_cyc && i_wb_stb);
// C1: A request with write and with read occur
cover(f_past_valid && !i_rst && !i_wb_rst && i_wb_cyc && i_wb_stb && i_wb_we);
cover(f_past_valid && !i_rst && !i_wb_rst && i_wb_cyc && i_wb_stb && !i_wb_we);
// C2: ACK happens during a request (basic progress)
cover(f_past_valid && !i_rst && !i_wb_rst && i_wb_cyc && i_wb_stb && o_wb_ack);
// C3: ACK same-cycle vs one-cycle-late (mirrors your R1 definition)
cover(f_past_valid && !i_rst && !i_wb_rst && (i_wb_cyc && i_wb_stb) && o_wb_ack);
cover(f_past_valid && !i_rst && !i_wb_rst && $past(i_wb_cyc && i_wb_stb) && o_wb_ack);
// C4: “wait state” from the slave POV: request persists without ACK
cover(f_past_valid && !i_rst && !i_wb_rst &&
$past(i_wb_cyc && i_wb_stb && !o_wb_ack) &&
(i_wb_cyc && i_wb_stb && !o_wb_ack));
// C5: Master ends a cycle (CYC drops) after at least one request
cover(f_past_valid && !i_rst && !i_wb_rst &&
$past(i_wb_cyc && i_wb_stb) && !i_wb_cyc);
end
wire unused = &{1'b0, o_wb_rdt};