jtag memory selectable

project.cfg

@@ -171,6 +171,7 @@ files_verilog       = rtl/toplevel/top_generic.v
                       rtl/serv/serv_rf_top.v
                       rtl/serv/serv_synth_wrapper.v
                       rtl/serv/serv_top.v
+                      rtl/serv/serving_ram.v
                     # QERV
                     #   rtl/qerv/serv_rf_top.v
                     #   rtl/qerv/serv_synth_wrapper.v

rtl/core/mcu.v

@@ -4,7 +4,8 @@
 module mcu #(
     parameter memfile = "",
     parameter memsize = 8192,
-    parameter sim = 1'b0
+    parameter sim = 1'b0,
+    parameter jtag = 1
 )(
     input wire i_clk,
     input wire i_rst,
@@ -149,7 +150,8 @@ module mcu #(
         .o_wb_ack(wb_mem_ack)
     );
 
-    memory #(
+    if(jtag) begin
+        memory_jtag #(
             .memfile(memfile),
             .depth(memsize),
             .sim(sim)
@@ -163,6 +165,21 @@ module mcu #(
             .o_rdata(sram_rdata),
             .o_core_reset(rst_mem_reason)
         );
+    end else begin
+        serving_ram #(
+            .memfile(memfile),
+            .depth(memsize),
+            .sim(sim)
+        ) mem (
+            .i_clk(i_clk),
+            .i_waddr(sram_waddr),
+            .i_wdata(sram_wdata),
+            .i_wen(sram_wen),
+            .i_raddr(sram_raddr),
+            .o_rdata(sram_rdata)
+        );
+        assign rst_mem_reason = 1'b0;
+    end
 
     mcu_peripherals peripherals (
         .i_clk(i_clk),

rtl/core/mem_jtag_writable.v

@@ -1,6 +1,6 @@
 `timescale 1ns/1ps
 
-module memory #(
+module memory_jtag #(
 	parameter memfile = "",
     parameter depth = 256,
 	parameter sim = 1'b0,

rtl/toplevel/top_generic.v

@@ -52,7 +52,8 @@ module top_generic #(
 
     mcu #(
         .memfile("../sw/sweep/sweep.hex"),
-        .sim(sim)
+        .sim(sim),
+        .jtag(1)
     ) mcu (
         .i_clk(clk_15),
         .i_rst(sys_reset),