jtag memory selectable

project.cfg

@@ -171,6 +171,7 @@ files_verilog       = rtl/toplevel/top_generic.v
                       rtl/serv/serv_rf_top.v
                       rtl/serv/serv_synth_wrapper.v
                       rtl/serv/serv_top.v
+                      rtl/serv/serving_ram.v
                     # QERV
                     #   rtl/qerv/serv_rf_top.v
                     #   rtl/qerv/serv_synth_wrapper.v