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New slave checker and updated gpio and gpio_banks

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This commit is contained in:
Joppe Blondel
2026-03-02 13:48:30 +01:00
parent a6a5c6ea3f
commit 628972ccaa
13 changed files with 334 additions and 245 deletions
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21
cores/wb/wb_gpio_banks/formal/formal_wb_gpio_banks.v
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@@ -1,31 +1,28 @@
`timescale 1ns/1ps
module formal_wb_gpio_banks #(
parameter integer NUM_BANKS = 2,
parameter [31:0] BASE_ADDR = 32'h00000000
parameter integer num_banks = 2,
);
(* gclk *) reg i_wb_clk;
(* gclk *) reg i_clk;
(* anyseq *) reg i_rst;
(* anyseq *) reg i_wb_rst;
(* anyseq *) reg [31:0] i_wb_adr;
(* anyseq *) reg [31:0] i_wb_dat;
(* anyseq *) reg [3:0] i_wb_sel;
(* anyseq *) reg i_wb_we;
(* anyseq *) reg i_wb_stb;
(* anyseq *) reg [NUM_BANKS*32-1:0] i_gpio;
(* anyseq *) reg [num_banks*32-1:0] i_gpio;
wire [31:0] o_wb_rdt;
wire o_wb_ack;
wire [NUM_BANKS*32-1:0] o_gpio;
wire [num_banks*32-1:0] o_gpio;
wire i_wb_cyc;
assign i_wb_cyc = i_wb_stb || o_wb_ack;
wb_gpio_banks #(
.NUM_BANKS(NUM_BANKS),
.BASE_ADDR(BASE_ADDR)
.num_banks(num_banks)
) dut (
.i_wb_clk(i_wb_clk),
.i_wb_rst(i_wb_rst),
.i_clk(i_clk),
.i_rst(i_rst),
.i_wb_adr(i_wb_adr),
.i_wb_dat(i_wb_dat),
.i_wb_sel(i_wb_sel),
@@ -38,9 +35,9 @@ module formal_wb_gpio_banks #(
);
formal_wb_slave_checker wb_checker (
.i_clk(i_wb_clk),
.i_clk(i_clk),
.i_rst(i_rst),
.i_wb_rst(i_wb_rst),
.i_wb_rst(i_rst),
.i_wb_adr(i_wb_adr),
.i_wb_dat(i_wb_dat),
.i_wb_sel(i_wb_sel),

2
cores/wb/wb_gpio_banks/formal/wb_gpio_banks.sby
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@@ -16,8 +16,10 @@ cover: smtbmc yices
prove: abc pdr
[script]
read -formal clog2.vh
{{"-formal"|gen_reads}}
prep -top {{top_level}}
[files]
src/joppeb_util_clog2_1.0/clog2.vh
{{files}}

108
cores/wb/wb_gpio_banks/rtl/wb_gpio_banks.v
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@@ -1,63 +1,61 @@
`default_nettype none
`include "clog2.vh"
module wb_gpio_banks #(
parameter integer NUM_BANKS = 4,
parameter [31:0] BASE_ADDR = 32'h8000_0000
) (
input wire i_wb_clk,
input wire i_wb_rst,
input wire [31:0] i_wb_adr,
input wire [31:0] i_wb_dat,
input wire [3:0] i_wb_sel,
input wire i_wb_we,
input wire i_wb_stb,
input wire [NUM_BANKS*32-1:0] i_gpio,
output reg [31:0] o_wb_rdt,
output reg o_wb_ack,
output wire [NUM_BANKS*32-1:0] o_gpio
parameter num_banks = 4
)(
input wire i_clk,
input wire i_rst,
input wire [31:0] i_wb_adr,
input wire [31:0] i_wb_dat,
output reg [31:0] o_wb_rdt,
input wire [3:0] i_wb_sel,
input wire i_wb_we,
input wire i_wb_cyc,
input wire i_wb_stb,
output wire o_wb_ack,
input wire [num_banks*32-1:0] i_gpio,
output wire [num_banks*32-1:0] o_gpio
);
localparam sw = `CLOG2(num_banks);
wire [num_banks-1:0] bank_sel;
wire [NUM_BANKS-1:0] bank_sel;
wire [NUM_BANKS-1:0] bank_stb;
wire [NUM_BANKS*32-1:0] bank_rdt;
wire [NUM_BANKS-1:0] bank_ack;
wire [num_banks-1:0] bank_ack;
wire [num_banks*32-1:0] bank_rdt;
genvar gi;
generate
for (gi = 0; gi < NUM_BANKS; gi = gi + 1) begin : gen_gpio
localparam [31:0] BANK_ADDR = BASE_ADDR + (gi * 4);
genvar gi;
generate
for(gi=0; gi<num_banks; gi=gi+1) begin : gen_gpio
localparam [2+sw-1:0] addr = gi*4;
assign bank_sel[gi] = (i_wb_adr[2+sw-1:0] == addr);
wb_gpio u_gpio(
.i_clk(i_clk),
.i_rst(i_rst),
.i_wb_adr(i_wb_adr),
.i_wb_dat(i_wb_dat),
.i_wb_cyc(i_wb_cyc & bank_sel[gi]),
.i_wb_stb(i_wb_stb & bank_sel[gi]),
.i_wb_we(i_wb_we),
.i_wb_sel(i_wb_sel),
.o_wb_ack(bank_ack[gi]),
.o_wb_rdt(bank_rdt[gi*32 +: 32]),
.i_gpio(i_gpio[gi*32 +: 32]),
.o_gpio(o_gpio[gi*32 +: 32])
);
end
endgenerate
assign bank_sel[gi] = (i_wb_adr == BANK_ADDR);
assign bank_stb[gi] = i_wb_stb & bank_sel[gi];
wb_gpio #(
.address(BANK_ADDR)
) u_gpio (
.i_wb_clk(i_wb_clk),
.i_wb_rst(i_wb_rst),
.i_wb_adr(i_wb_adr),
.i_wb_dat(i_wb_dat),
.i_wb_sel(i_wb_sel),
.i_wb_we(i_wb_we),
.i_wb_stb(bank_stb[gi]),
.i_gpio(i_gpio[gi*32 +: 32]),
.o_wb_rdt(bank_rdt[gi*32 +: 32]),
.o_wb_ack(bank_ack[gi]),
.o_gpio(o_gpio[gi*32 +: 32])
);
end
endgenerate
integer bi;
always @* begin
o_wb_rdt = 32'h0000_0000;
o_wb_ack = 1'b0;
for (bi = 0; bi < NUM_BANKS; bi = bi + 1) begin
if (bank_sel[bi]) begin
o_wb_rdt = bank_rdt[bi*32 +: 32];
o_wb_ack = bank_ack[bi];
end
end
end
integer bi;
always @* begin
o_wb_rdt = 0;
o_wb_ack = 0;
for(bi=0; bi<num_banks; bi=bi+1) begin
if(bank_sel[bi]) begin
o_wb_rdt = bank_rdt[bi*32 +: 32];
o_wb_ack = bank_ack[bi];
end
end
end;
endmodule

1
cores/wb/wb_gpio_banks/wb_gpio_banks.core
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@@ -7,6 +7,7 @@ filesets:
rtl:
depend:
- joppeb:wb:wb_gpio
- joppeb:util:clog2
files:
- rtl/wb_gpio_banks.v
file_type: verilogSource