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New slave checker and updated gpio and gpio_banks

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This commit is contained in:
Joppe Blondel
2026-03-02 13:48:30 +01:00
parent a6a5c6ea3f
commit 628972ccaa
13 changed files with 334 additions and 245 deletions
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28
cores/wb/wb_gpio/formal/formal_wb_gpio.v
View File

@@ -1,35 +1,29 @@
`timescale 1ns/1ps
module formal_wb_gpio #(
parameter [31:0] address = 32'h00000000
);
module formal_wb_gpio;
(* gclk *) reg i_wb_clk;
(* anyseq *) reg i_rst;
(* anyseq *) reg i_wb_rst;
(* anyseq *) reg [31:0] i_wb_adr;
(* anyseq *) reg [31:0] i_wb_dat;
(* anyseq *) reg [3:0] i_wb_sel;
(* anyseq *) reg i_wb_we;
(* anyseq *) reg i_wb_stb;
(* anyseq *) reg i_wb_cyc;
(* anyseq *) reg [31:0] i_gpio;
wire [31:0] o_wb_rdt;
wire o_wb_ack;
wire [31:0] o_gpio;
wire i_wb_cyc;
reg f_past_valid;
assign i_wb_cyc = i_wb_stb || o_wb_ack;
wb_gpio #(
.address(address)
) dut (
.i_wb_clk(i_wb_clk),
.i_wb_rst(i_wb_rst),
wb_gpio dut (
.i_clk(i_wb_clk),
.i_rst(i_wb_rst),
.i_wb_adr(i_wb_adr),
.i_wb_dat(i_wb_dat),
.i_wb_sel(i_wb_sel),
.i_wb_we(i_wb_we),
.i_wb_stb(i_wb_stb),
.i_wb_cyc(i_wb_cyc),
.i_gpio(i_gpio),
.o_wb_rdt(o_wb_rdt),
.o_wb_ack(o_wb_ack),
@@ -38,7 +32,7 @@ module formal_wb_gpio #(
formal_wb_slave_checker wb_checker (
.i_clk(i_wb_clk),
.i_rst(i_rst),
.i_rst(i_wb_rst),
.i_wb_rst(i_wb_rst),
.i_wb_adr(i_wb_adr),
.i_wb_dat(i_wb_dat),
@@ -56,9 +50,13 @@ module formal_wb_gpio #(
f_past_valid <= 1'b1;
// R1: reads return the sampled GPIO input on the following cycle
if (f_past_valid && !$past(i_wb_rst) && !i_wb_rst && $past(i_wb_stb) && !$past(i_wb_we)) begin
if(f_past_valid &&
!i_wb_rst && $past(!i_wb_rst) &&
o_wb_ack &&
$past(i_wb_sel)==4'hf && i_wb_sel==4'hf &&
$past(i_wb_cyc & i_wb_stb & !i_wb_we) &&
(i_wb_cyc & i_wb_stb & !i_wb_we))
assert(o_wb_rdt == $past(i_gpio));
end
// R2: reset clears the output register and read data register
if (f_past_valid && $past(i_wb_rst)) begin

95
cores/wb/wb_gpio/rtl/wb_gpio.v
View File

@@ -1,56 +1,53 @@
module wb_gpio #(
parameter address = 32'h00000000
)(
input wire i_wb_clk,
input wire i_wb_rst, // optional; tie low if unused
input wire [31:0] i_wb_adr, // optional; can ignore for single-reg
input wire [31:0] i_wb_dat,
input wire [3:0] i_wb_sel,
input wire i_wb_we,
input wire i_wb_stb,
input wire [31:0] i_gpio,
module wb_gpio (
input wire i_clk,
input wire i_rst,
output reg [31:0] o_wb_rdt,
output reg o_wb_ack,
output reg [31:0] o_gpio
input wire [31:0] i_wb_adr,
input wire [31:0] i_wb_dat,
output reg [31:0] o_wb_rdt,
input wire [3:0] i_wb_sel,
input wire i_wb_we,
input wire i_wb_cyc,
input wire i_wb_stb,
output wire o_wb_ack,
input wire [31:0] i_gpio,
output wire [31:0] o_gpio
);
// Registers
reg [31:0] gpo;
wire [31:0] gpi;
assign o_gpio = gpo;
assign gpi = i_gpio;
initial o_gpio <= 32'h00000000;
initial o_wb_rdt <= 32'h00000000;
reg wb_ack = 0;
assign o_wb_ack = wb_ack & i_wb_cyc & i_wb_stb;
wire addr_check;
assign addr_check = (i_wb_adr == address);
always @(posedge i_clk) begin
if(i_rst) begin
gpo <= 0;
wb_ack <= 0;
o_wb_rdt <= 0;
end else begin
// Ack generation
wb_ack <= i_wb_cyc & i_wb_stb & !wb_ack;
// One-cycle ACK pulse per request (works even if stb stays high)
initial o_wb_ack <= 1'b0;
always @(posedge i_wb_clk) begin
if (i_wb_rst) begin
o_wb_ack <= 1'b0;
end else begin
o_wb_ack <= i_wb_stb & ~o_wb_ack; // pulse while stb asserted
end
end
// Read data (combinational or registered; registered here)
always @(posedge i_wb_clk) begin
if (i_wb_rst) begin
o_wb_rdt <= 32'h0;
end else if (i_wb_stb && !i_wb_we) begin
o_wb_rdt <= i_gpio;
end
end
// Write latch (update on the acknowledged cycle)
always @(posedge i_wb_clk) begin
if (i_wb_rst) begin
o_gpio <= 32'h0;
end else if (i_wb_stb && i_wb_we && addr_check && (i_wb_stb & ~o_wb_ack)) begin
// Apply byte enables (so sb works if the master uses sel)
if (i_wb_sel[0]) o_gpio[7:0] <= i_wb_dat[7:0];
if (i_wb_sel[1]) o_gpio[15:8] <= i_wb_dat[15:8];
if (i_wb_sel[2]) o_gpio[23:16] <= i_wb_dat[23:16];
if (i_wb_sel[3]) o_gpio[31:24] <= i_wb_dat[31:24];
end
end
// Read cycle
if(i_wb_cyc && i_wb_stb && !i_wb_we) begin
if(i_wb_sel[0]) o_wb_rdt[7:0] <= gpi[7:0];
if(i_wb_sel[1]) o_wb_rdt[15:8] <= gpi[15:8];
if(i_wb_sel[2]) o_wb_rdt[23:16] <= gpi[23:16];
if(i_wb_sel[3]) o_wb_rdt[31:24] <= gpi[31:24];
end
// write cycle
if(i_wb_cyc && i_wb_stb && i_wb_we) begin
if(i_wb_sel[0]) gpo[7:0] <= i_wb_dat[7:0];
if(i_wb_sel[1]) gpo[15:8] <= i_wb_dat[15:8];
if(i_wb_sel[2]) gpo[23:16] <= i_wb_dat[23:16];
if(i_wb_sel[3]) gpo[31:24] <= i_wb_dat[31:24];
end
end
end
endmodule

10
cores/wb/wb_gpio/wb_gpio.core
View File

@@ -25,8 +25,6 @@ targets:
filesets:
- rtl
toplevel: wb_gpio
parameters:
- address
formal:
default_tool: symbiyosys
@@ -35,11 +33,3 @@ targets:
- formal_rtl
- formal_cfg
toplevel: formal_wb_gpio
parameters:
- address
parameters:
address:
datatype: int
description: Wishbone address matched by this peripheral
paramtype: vlogparam