Added missing signal modules

2026-03-02 19:28:36 +01:00
parent 50f71a2985
commit 4e3521e94a
20 changed files with 795 additions and 67 deletions
--- a/cores/system/test/rtl/toplevel.v
+++ b/cores/system/test/rtl/toplevel.v
@@ -81,12 +81,12 @@ module toplevel #(
        .CLK_HZ(15_000_000),
        .FS_HZ(80_000)
    ) nco (
-        .clk    (clk_15),
-        .rst_n  (sys_resetn),
-        .freq_hz(GPIO_A),
-        .sin_q15(sin_q15),
-        .cos_q15(),
-        .clk_en (clk_en)
+        .i_clk    (clk_15),
+        .i_rst_n  (sys_resetn),
+        .i_freq_hz(GPIO_A),
+        .o_sin_q15(sin_q15),
+        .o_cos_q15(),
+        .o_clk_en (clk_en)
    );

    reg [5:0] dac_code;