initial commit

HW/toplevel.v

@@ -0,0 +1,20 @@
+`timescale 1ns/1ps
+
+module toplevel(
+    input wire clk,
+    input wire reset_n,
+    input wire button,
+    output wire led
+);
+    reg led_v;
+
+    always @(posedge clk or negedge reset_n) begin
+      if (!reset_n) begin
+        led_v <= 1'b0;
+      end else begin
+        led_v <= button;
+      end
+    end
+    assign led = led_v;
+
+endmodule