Trigger selection

This commit is contained in:
2026-03-05 16:24:29 +01:00
parent cfdec1aec7
commit 08c0f6967b
2 changed files with 59 additions and 21 deletions

View File

@@ -53,6 +53,12 @@ def parse_args() -> argparse.Namespace:
default=None,
help="Optional trigger threshold (16-bit, signal_a rising crossing). If omitted, triggering is disabled.",
)
parser.add_argument(
"--trigger-channel",
choices=["a", "b", "c", "d"],
default="a",
help="Trigger source channel when triggering is enabled",
)
parser.add_argument(
"--unsigned",
action="store_true",
@@ -81,15 +87,20 @@ def parse_args() -> argparse.Namespace:
def capture_once(bridge, args: argparse.Namespace) -> list[tuple[int, int, int, int]]:
samples = []
frame_count = args.depth
trigger_channel_map = {"a": 0, "b": 1, "c": 2, "d": 3}
trigger_channel = trigger_channel_map[args.trigger_channel]
if args.trigger_value is None:
print("[signal_scope] Arming scope with trigger disabled...")
bridge.write32(REG_CONTROL, 0x1) # bit0: arm pulse, bit1: trigger enable=0
else:
trig_val = args.trigger_value & 0xFFFF
print(f"[signal_scope] Config trigger: trig_val=0x{trig_val:04x}, source=signal_a rising")
print(
f"[signal_scope] Config trigger: trig_val=0x{trig_val:04x}, "
f"source=signal_{args.trigger_channel} rising"
)
bridge.write32(REG_TRIG_VAL, trig_val)
print("[signal_scope] Arming scope with trigger enabled...")
bridge.write32(REG_CONTROL, 0x3) # bit0: arm pulse, bit1: trigger enable
bridge.write32(REG_CONTROL, 0x3 | (trigger_channel << 2)) # bit0: arm, bit1: trig_en, bits[3:2]: channel
# Wait until the new arm command is active, then wait for its trigger event.
while (bridge.read32(REG_STATUS) & 0x4) == 0: