tape training

This commit is contained in:
Joppe Blondel
2026-10-03 17:30:43 +02:00
parent 5897e55094
commit 9823a05ffe
8 changed files with 1085 additions and 43 deletions
+12 -1
View File
@@ -5,6 +5,8 @@
#define UART_CTC_CARD_BASE 0x20
#define CTC_BASE (UART_CTC_CARD_BASE + 0x00)
#define CTC_CHANNEL_0 (CTC_BASE + 0)
#define CTC_CHANNEL_1 (CTC_BASE + 1)
#define CTC_CHANNEL_2 (CTC_BASE + 2)
#define CTC_CHANNEL_3 (CTC_BASE + 3)
#define UART_BASE (UART_CTC_CARD_BASE + 0x04)
#define UART_CONTROL (UART_BASE + 0)
@@ -76,6 +78,16 @@ void bios_init(void)
buffer_init(&rx_buf);
buffer_init(&tx_buf);
/* A CPU-only reset does not necessarily reset the external CTC. Stop and
disable every channel before rebuilding the UART clock/IRQ path. */
io_out(CTC_CHANNEL_0, 0x03);
io_out(CTC_CHANNEL_1, 0x03);
io_out(CTC_CHANNEL_2, 0x03);
io_out(CTC_CHANNEL_3, 0x03);
/* The 6850 has no reset input; CR1:CR0 = 11 is its master reset. */
io_out(UART_CONTROL, 0b00000011);
io_out(CTC_CHANNEL_0, 0x57);
io_out(CTC_CHANNEL_0, 13);
io_out(CTC_CHANNEL_3, 0b11001111);
@@ -84,7 +96,6 @@ void bios_init(void)
io_out(CTC_CHANNEL_0, 0x40);
uart_tx_busy = 0;
io_out(UART_CONTROL, 0b00000011);
io_out(UART_CONTROL, 0b10010101);
enable_interrupts();
}