tape training
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@@ -5,6 +5,8 @@
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#define UART_CTC_CARD_BASE 0x20
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#define CTC_BASE (UART_CTC_CARD_BASE + 0x00)
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#define CTC_CHANNEL_0 (CTC_BASE + 0)
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#define CTC_CHANNEL_1 (CTC_BASE + 1)
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#define CTC_CHANNEL_2 (CTC_BASE + 2)
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#define CTC_CHANNEL_3 (CTC_BASE + 3)
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#define UART_BASE (UART_CTC_CARD_BASE + 0x04)
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#define UART_CONTROL (UART_BASE + 0)
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@@ -76,6 +78,16 @@ void bios_init(void)
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buffer_init(&rx_buf);
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buffer_init(&tx_buf);
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/* A CPU-only reset does not necessarily reset the external CTC. Stop and
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disable every channel before rebuilding the UART clock/IRQ path. */
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io_out(CTC_CHANNEL_0, 0x03);
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io_out(CTC_CHANNEL_1, 0x03);
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io_out(CTC_CHANNEL_2, 0x03);
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io_out(CTC_CHANNEL_3, 0x03);
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/* The 6850 has no reset input; CR1:CR0 = 11 is its master reset. */
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io_out(UART_CONTROL, 0b00000011);
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io_out(CTC_CHANNEL_0, 0x57);
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io_out(CTC_CHANNEL_0, 13);
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io_out(CTC_CHANNEL_3, 0b11001111);
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@@ -84,7 +96,6 @@ void bios_init(void)
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io_out(CTC_CHANNEL_0, 0x40);
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uart_tx_busy = 0;
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io_out(UART_CONTROL, 0b00000011);
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io_out(UART_CONTROL, 0b10010101);
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enable_interrupts();
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}
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