Initial commit

2026-09-28 13:17:35 +02:00
commit 67ec3c9a65
7 changed files with 403 additions and 0 deletions
@@ -0,0 +1,175 @@
+STACK_TOP = 0xFFFF
+DELAY_LOOPS_PER_MS = 40
+
+        .globl _main
+        .globl _delay_ms
+        .globl _io_out
+        .globl _io_in
+        .globl _enable_interrupts
+        .globl _disable_interrupts
+        .globl s__DATA
+        .globl l__DATA
+        .globl s__INITIALIZER
+        .globl s__INITIALIZED
+        .globl l__INITIALIZER
+
+.area _ITABLE (ABS)
+
+.org 0x00
+        jp init
+.org 0x08
+        reti
+.org 0x10
+        reti
+.org 0x18
+        reti
+.org 0x20
+        reti
+.org 0x28
+        reti
+.org 0x30
+        reti
+.org 0x38
+        reti
+
+; ITABLE
+.org 0x40
+        .dw ctc_isr          ; CTC channel 0: vector 0x40
+        .dw ctc_isr          ; CTC channel 1: vector 0x42
+        .dw ctc_isr          ; CTC channel 2: vector 0x44
+        .dw uart_isr         ; CTC channel 3: vector 0x46
+
+.area _HOME
+init:
+        di
+        ld sp, #STACK_TOP
+
+        call gsinit
+
+        ; Setup interrupt mode 2
+        xor a
+        ld i, a
+        im 2
+        call _main
+
+hang:
+        jr hang
+
+.area _GSINIT
+gsinit:
+        ld bc, #l__INITIALIZER
+        ld a, b
+        or c
+        jr z, zero_data
+
+        ld de, #s__INITIALIZED
+        ld hl, #s__INITIALIZER
+        ldir
+
+zero_data:
+        ld bc, #l__DATA
+        ld a, b
+        or c
+        jr z, gsinit_done
+
+        ld hl, #s__DATA
+        xor a
+
+clear_loop:
+        xor a                         ; BC loop test below changes A
+        ld (hl), a
+        inc hl
+        dec bc
+        ld a, b
+        or c
+        jr nz, clear_loop
+
+gsinit_done:
+.area _GSFINAL
+        ret
+
+.area _CODE
+
+.macro MAKE_ISR entry, handler
+        .globl handler
+entry:
+        push    af
+        push    bc
+        push    de
+        push    hl
+        push    ix
+        push    iy
+
+        ex      af, af'
+        push    af
+        exx
+        push    bc
+        push    de
+        push    hl
+
+        call    handler
+
+        pop     hl
+        pop     de
+        pop     bc
+        exx
+        pop     af
+        ex      af, af'
+
+        pop     iy
+        pop     ix
+        pop     hl
+        pop     de
+        pop     bc
+        pop     af
+        ei
+        reti
+.endm
+
+MAKE_ISR ctc_isr, _ctc_interrupt
+MAKE_ISR uart_isr, _uart_interrupt
+
+_enable_interrupts::
+        ei
+        ret
+
+_disable_interrupts::
+        di
+        ret
+
+; Write a byte to an I/O port.
+; Input: A = port address, L = data byte.
+_io_out::
+        ld      c, a
+        ld      a, l
+        out     (c), a
+        ret
+
+; Read a byte from an I/O port.
+; Input: A = port address.
+; Return: A = data byte.
+_io_in::
+        ld      c, a
+        in      a, (c)
+        ret
+
+; Approximate millisecond delay.
+; Input: HL = delay in milliseconds.
+_delay_ms::
+        ld      a, h
+        or      l
+        ret     z
+delay_ms_outer$:
+        push    hl
+        ld      hl, #DELAY_LOOPS_PER_MS
+delay_ms_inner$:
+        dec     hl
+        ld      a, h
+        or      l
+        jr      nz, delay_ms_inner$
+        pop     hl
+        dec     hl
+        ld      a, h
+        or      l
+        jr      nz, delay_ms_outer$
+        ret