start of tape loading. hw works and have a generation script
This commit is contained in:
Joppe Blondel
+16
-12
@@ -7,25 +7,29 @@ directory instead of accessing the UART hardware directly.
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The current allocation is:
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- `1000-180C`: Tiny BASIC
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- `180D-7FFF`: available for more applications (`1900` is the next convenient
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- `1400-1C0C`: Tiny BASIC
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- `1C0D-2FFF`: available
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- `3000-301D`: tape loader
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- `301E-7FFF`: available for more applications (`3100` is the next convenient
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aligned origin)
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The resident BIOS and monitor own high RAM at `C000-FFFF`. Tiny BASIC owns
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`8000-BFFF` for its workspace and stack. A future application may reuse Tiny
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BASIC's lower-RAM allocation because ROM applications run one at a time, but it
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must leave `C000-FFFF` untouched.
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`8000-BFFF` for its workspace and stack. Applications may reuse this lower-RAM
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allocation because they run one at a time, but they must leave `C000-FFFF`
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untouched.
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Applications using the interrupt-driven console must leave interrupt mode 2,
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the `I` register, and the BIOS UART/CTC configuration intact. They may return
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normally if they preserve the caller's stack, or jump to `BIOS_MONITOR` for a
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non-returning monitor warm start after replacing the stack pointer.
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Use `BIOS_BANK` and `BIOS_ROM_DISABLE` for the write-only banking latch rather
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than writing port `00` directly. The BIOS keeps the ROM-disable state when the
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RAM bank selection changes. A ROM application must not expect a normal `RET`
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after it maps out the ROM containing its return address.
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Use `BIOS_BANK`, `BIOS_ROM_DISABLE`, and `BIOS_ROM_ENABLE` for the write-only
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banking latch rather than writing port `00` directly. The BIOS keeps the
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ROM-disable state when the RAM bank selection changes. A ROM application must
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not expect a normal `RET` after it maps out the ROM containing its return
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address.
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To add an application, add its assembler target and ROM offset to the Makefile,
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overlay its binary in the `monitor.prog.bin` recipe, and add a monitor command
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or use `G address` to launch it.
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Application origins and the resident-memory layout are defined centrally in
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`rom_layout.mk`. The build turns that file into C and assembly includes. To add
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an application, add its address there, add its build and overlay rules to the
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Makefile, and add a monitor command or use `G address` to launch it.
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@@ -0,0 +1,199 @@
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Name casette;
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PartNo 00;
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Date 2026-10-03;
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Revision 01;
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Designer joppe;
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Company unknown;
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Assembly None;
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Location unknown;
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Device g22v10;
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/* ------------------------------------------------------------
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Constants
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------------------------------------------------------------ */
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ar = 'b'0;
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sp = 'b'0;
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/* ------------------------------------------------------------
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Pin assignments
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Physical signals IOSEL, RD and WR are active-low.
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Their polarity is expressed in the equations with !.
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------------------------------------------------------------ */
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/* inputs */
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PIN 1 = CLK;
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PIN 2 = A1;
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PIN 3 = A2;
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PIN 4 = IOSEL;
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PIN 5 = RD;
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PIN 6 = A0;
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PIN 7 = COMP;
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PIN 8 = WR;
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/* data bus */
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PIN 14 = D0;
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PIN 15 = D1;
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PIN 16 = D2;
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PIN 17 = D3;
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PIN 18 = D4;
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PIN 19 = D5;
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PIN 20 = D6;
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PIN 21 = D7;
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/* registered output */
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PIN 22 = LED;
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/* ------------------------------------------------------------
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Read register at offset 0
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Conditions:
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/IOSEL = 0
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/RD = 0
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/WR = 1
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A2:A0 = 000
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Result:
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D0 = COMP
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D7..D1 = 0
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------------------------------------------------------------ */
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D0 = COMP;
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D1 = 'b'0;
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D2 = 'b'0;
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D3 = 'b'0;
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D4 = 'b'0;
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D5 = 'b'0;
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D6 = 'b'0;
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D7 = 'b'0;
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D0.OE =
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!IOSEL
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& !RD
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& WR
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& !A2
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& !A1
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& !A0;
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D1.OE =
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!IOSEL
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& !RD
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& WR
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& !A2
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& !A1
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& !A0;
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D2.OE =
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!IOSEL
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& !RD
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& WR
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& !A2
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& !A1
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& !A0;
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D3.OE =
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!IOSEL
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& !RD
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& WR
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& !A2
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& !A1
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& !A0;
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D4.OE =
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!IOSEL
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& !RD
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& WR
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& !A2
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& !A1
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& !A0;
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D5.OE =
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!IOSEL
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& !RD
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& WR
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& !A2
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& !A1
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& !A0;
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D6.OE =
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!IOSEL
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& !RD
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& WR
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& !A2
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& !A1
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& !A0;
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D7.OE =
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!IOSEL
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& !RD
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& WR
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& !A2
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& !A1
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& !A0;
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/* ------------------------------------------------------------
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Writable LED register
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Write conditions:
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/IOSEL = 0
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/RD = 1
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/WR = 0
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A2:A0 = 000
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During such a write:
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LED.D = D0
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Otherwise:
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LED.D = LED
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Pin 1 (CLK) clocks the registered macrocell.
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------------------------------------------------------------ */
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LED.D =
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(
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!IOSEL
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& RD
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& !WR
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& !A2
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& !A1
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& !A0
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& D0
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)
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#
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(
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(
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IOSEL
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# !RD
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# WR
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# A2
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# A1
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# A0
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)
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& LED
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);
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LED.ar = ar;
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LED.sp = sp;
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@@ -0,0 +1,54 @@
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CUPL(WM) 5.0a Serial# MW-10400000
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Device g22v10 Library DLIB-h-40-1
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Created Sat Oct 03 16:22:02 2026
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Name casette
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Partno 00
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Revision 01
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Date 2026-10-03
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Designer joppe
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Company unknown
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Assembly None
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Location unknown
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*QP24
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*QF5892
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*G1
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*F0
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*L00416 00000000000000000000000011111111
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*L00448 11111111111111111111111111111111
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*L00480 11111111101110111011011110111111
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*L00512 10111111110111111111111011110111
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*L00544 11111111111111111111111111111111
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*L00576 11101111111110111111111111111111
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*L00608 11111111111111101111111111111111
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*L00640 11110111111111111111111111100111
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*L00672 11111111111111111111111111111111
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*L00704 11110110111111111111111111111111
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*L00736 11111111111111111110111111111111
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*L00768 01111111111111111111111100000000
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*L00896 00000000000000000000000000001111
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*L00928 10111011101110111011111101111111
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*L00960 11111111000000000000000000000000
|
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*L01472 00000000000000000000000011111011
|
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*L01504 10111011101110111111011111111111
|
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*L01536 11110000000000000000000000000000
|
||||
*L02144 00000000000011111011101110111011
|
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*L02176 10111111011111111111111100000000
|
||||
*L02880 00000000000000000000000011111011
|
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*L02912 10111011101110111111011111111111
|
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*L02944 11110000000000000000000000000000
|
||||
*L03648 00001111101110111011101110111111
|
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*L03680 01111111111111110000000000000000
|
||||
*L04288 00000000000000000000000011111011
|
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*L04320 10111011101110111111011111111111
|
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*L04352 11110000000000000000000000000000
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*L04864 00000000000000000000111110111011
|
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*L04896 10111011101111110111111111111111
|
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*L05344 00000000000000000000000011111011
|
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*L05376 10111011101110111111011111111111
|
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*L05408 11111111111111111111111111110111
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*L05440 11111111111111110000000000000000
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*L05792 00000000000000000010111111111111
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*L05824 11110011000000110000000000000000
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*C5BE4
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*6A87
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@@ -0,0 +1,189 @@
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#!/usr/bin/env python3
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"""
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z80_tape_encode.py
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Encode a binary file as a mono PCM WAV using robust two-tone Manchester FSK.
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Defaults:
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- 48 kHz sample rate
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- 600 bit/s
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- 2 kHz / 4 kHz tones
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- Manchester FSK:
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0 -> low tone for half a bit, then high tone
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1 -> high tone for half a bit, then low tone
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- 1 second 4 kHz leader
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- 64 bytes of 0x55 preamble
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- 256-byte CRC-protected blocks
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- CRC-16/CCITT-FALSE
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"""
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from __future__ import annotations
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import argparse
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import math
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import struct
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import wave
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from pathlib import Path
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SYNC = b"\xD3\x91"
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PREAMBLE_BYTE = 0x55
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def crc16_ccitt_false(data: bytes) -> int:
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crc = 0xFFFF
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for byte in data:
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crc ^= byte << 8
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for _ in range(8):
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crc = ((crc << 1) ^ 0x1021) & 0xFFFF if (crc & 0x8000) else (crc << 1) & 0xFFFF
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return crc
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class FSKWriter:
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def __init__(self, sample_rate: int, baud: int, f_low: float, f_high: float, amplitude: float):
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if sample_rate % (2 * baud) != 0:
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raise ValueError("sample_rate must be divisible by 2*baud")
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self.sample_rate = sample_rate
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self.baud = baud
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self.f_low = f_low
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self.f_high = f_high
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self.amplitude = amplitude
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self.samples_per_half_bit = sample_rate // (2 * baud)
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self.phase = 0.0
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self.samples = bytearray()
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def _tone(self, frequency: float, sample_count: int) -> None:
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phase_step = 2.0 * math.pi * frequency / self.sample_rate
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scale = int(32767 * self.amplitude)
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phase = self.phase
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out = self.samples
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for _ in range(sample_count):
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sample = int(round(scale * math.sin(phase)))
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out.extend(struct.pack("<h", sample))
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phase += phase_step
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if phase >= 2.0 * math.pi:
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phase -= 2.0 * math.pi
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self.phase = phase
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def leader(self, seconds: float) -> None:
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self._tone(self.f_high, round(seconds * self.sample_rate))
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def bit(self, value: int) -> None:
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# Manchester-FSK:
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# 0 = low -> high
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# 1 = high -> low
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if value:
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first, second = self.f_high, self.f_low
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else:
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first, second = self.f_low, self.f_high
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self._tone(first, self.samples_per_half_bit)
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self._tone(second, self.samples_per_half_bit)
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||||
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||||
def byte(self, value: int) -> None:
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# MSB first
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for bit_no in range(7, -1, -1):
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self.bit((value >> bit_no) & 1)
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||||
|
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def bytes(self, data: bytes) -> None:
|
||||
for value in data:
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||||
self.byte(value)
|
||||
|
||||
|
||||
def make_block(sequence: int, payload: bytes) -> bytes:
|
||||
header = struct.pack("<HH", sequence & 0xFFFF, len(payload))
|
||||
crc = crc16_ccitt_false(header + payload)
|
||||
return SYNC + header + payload + struct.pack("<H", crc)
|
||||
|
||||
|
||||
def make_eof_block(sequence: int) -> bytes:
|
||||
header = struct.pack("<HH", sequence & 0xFFFF, 0)
|
||||
crc = crc16_ccitt_false(header)
|
||||
return SYNC + header + struct.pack("<H", crc)
|
||||
|
||||
|
||||
def encode(
|
||||
input_path: Path,
|
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output_path: Path,
|
||||
*,
|
||||
sample_rate: int = 48_000,
|
||||
baud: int = 600,
|
||||
f_low: float = 2_000.0,
|
||||
f_high: float = 4_000.0,
|
||||
leader_seconds: float = 1.0,
|
||||
preamble_bytes: int = 64,
|
||||
block_size: int = 256,
|
||||
amplitude: float = 0.75,
|
||||
) -> None:
|
||||
data = input_path.read_bytes()
|
||||
|
||||
if not 0 < amplitude <= 1.0:
|
||||
raise ValueError("amplitude must be > 0 and <= 1")
|
||||
if not 1 <= block_size <= 0xFFFF:
|
||||
raise ValueError("block_size must be in 1..65535")
|
||||
|
||||
writer = FSKWriter(sample_rate, baud, f_low, f_high, amplitude)
|
||||
|
||||
writer.leader(leader_seconds)
|
||||
writer.bytes(bytes([PREAMBLE_BYTE]) * preamble_bytes)
|
||||
|
||||
sequence = 0
|
||||
for start in range(0, len(data), block_size):
|
||||
payload = data[start:start + block_size]
|
||||
writer.bytes(make_block(sequence, payload))
|
||||
sequence = (sequence + 1) & 0xFFFF
|
||||
|
||||
writer.bytes(make_eof_block(sequence))
|
||||
|
||||
with wave.open(str(output_path), "wb") as wav:
|
||||
wav.setnchannels(1)
|
||||
wav.setsampwidth(2)
|
||||
wav.setframerate(sample_rate)
|
||||
wav.writeframes(writer.samples)
|
||||
|
||||
duration = len(writer.samples) / 2 / sample_rate
|
||||
|
||||
print(f"Input: {input_path}")
|
||||
print(f"Output: {output_path}")
|
||||
print(f"Input bytes: {len(data)}")
|
||||
print(f"Bit rate: {baud} bit/s")
|
||||
print(f"Tones: {f_low:g} Hz / {f_high:g} Hz")
|
||||
print(f"Sample rate: {sample_rate} Hz")
|
||||
print(f"Half-bit: {writer.samples_per_half_bit} samples")
|
||||
print(f"Block size: {block_size} bytes")
|
||||
print(f"WAV duration: {duration:.2f} s")
|
||||
|
||||
|
||||
def main() -> None:
|
||||
parser = argparse.ArgumentParser(description="Encode a binary file as Manchester two-tone FSK WAV.")
|
||||
parser.add_argument("input", type=Path, help="binary input file")
|
||||
parser.add_argument("output", type=Path, nargs="?", help="output WAV; default: INPUT.wav")
|
||||
parser.add_argument("--baud", type=int, default=600)
|
||||
parser.add_argument("--low", type=float, default=2000.0, help="low tone in Hz")
|
||||
parser.add_argument("--high", type=float, default=4000.0, help="high tone in Hz")
|
||||
parser.add_argument("--sample-rate", type=int, default=48000)
|
||||
parser.add_argument("--leader", type=float, default=1.0, help="leader seconds")
|
||||
parser.add_argument("--preamble", type=int, default=64, help="number of 0x55 preamble bytes")
|
||||
parser.add_argument("--block-size", type=int, default=64)
|
||||
parser.add_argument("--amplitude", type=float, default=0.75)
|
||||
|
||||
args = parser.parse_args()
|
||||
output = args.output or args.input.with_name(args.input.name + ".wav")
|
||||
|
||||
encode(
|
||||
args.input,
|
||||
output,
|
||||
sample_rate=args.sample_rate,
|
||||
baud=args.baud,
|
||||
f_low=args.low,
|
||||
f_high=args.high,
|
||||
leader_seconds=args.leader,
|
||||
preamble_bytes=args.preamble,
|
||||
block_size=args.block_size,
|
||||
amplitude=args.amplitude,
|
||||
)
|
||||
|
||||
|
||||
if __name__ == "__main__":
|
||||
main()
|
||||
@@ -0,0 +1,50 @@
|
||||
.include "bios.inc"
|
||||
|
||||
.area TAPELOAD (ABS)
|
||||
.org TAPE_LOADER_ROM_ADDRESS
|
||||
|
||||
COMP_PORT = 0x18
|
||||
|
||||
WORK_BASE = 0x0B000
|
||||
LOAD_START = 0x08000
|
||||
LOAD_LIMIT_HI = 0x0B0
|
||||
STACK_TOP = 0x0BFFF
|
||||
|
||||
OLD_SP = WORK_BASE+0x00
|
||||
|
||||
start:
|
||||
ld (OLD_SP), sp
|
||||
ld sp, #STACK_TOP
|
||||
|
||||
di
|
||||
|
||||
poll_loop:
|
||||
|
||||
; Read from the hardware port COMP_PORT
|
||||
in a, (COMP_PORT)
|
||||
out (COMP_PORT), a
|
||||
|
||||
; Save the raw port status in register B
|
||||
ld b, a
|
||||
|
||||
; Print a carriage return '\r' (ASCII 0x0D)
|
||||
ld a, #0x0D
|
||||
call BIOS_PUTC
|
||||
|
||||
; Restore the port status and isolate the relevant bit
|
||||
; (Assuming bit 0 determines 0 or 1; adjust 'and' mask if it is a different bit)
|
||||
ld a, b
|
||||
and #0x01
|
||||
|
||||
; Convert the binary 0 or 1 into ASCII '0' (0x30) or '1' (0x31)
|
||||
add a, #0x30
|
||||
|
||||
; Print the '0' or '1' character
|
||||
call BIOS_PUTC
|
||||
|
||||
; Infinite loop: poll continuously
|
||||
jr poll_loop
|
||||
|
||||
ld sp, (OLD_SP)
|
||||
ei
|
||||
ret
|
||||
@@ -42,7 +42,7 @@
|
||||
; Adapted to work with GNU z80asm
|
||||
; Added interrupt handling
|
||||
; Notes for this monitor port:
|
||||
; Converted to sdasz80 syntax and linked as a ROM application at 1000.
|
||||
; Converted to sdasz80 syntax and linked as a ROM application at 2200.
|
||||
; Fixed-page RST calls were converted to local CALLs.
|
||||
; UART access uses the resident BIOS ABI at C050/C053.
|
||||
|
||||
@@ -102,7 +102,7 @@ STKLMT = 0xB078 ;LOWEST ALLOWED STACK ADDRESS
|
||||
;*************************************************************
|
||||
|
||||
.area TINYBASIC (ABS)
|
||||
.org 0x1000
|
||||
.org TINYBASIC_ROM_ADDRESS
|
||||
main:
|
||||
START:
|
||||
LD SP,#STACK ;*** COLD START ***
|
||||
Reference in New Issue
Block a user